Configure Aurora 8b10b in Vivado 2019.2 to generate 3-bit tkeep

[Cesar0182]

Greetings, tell you that a couple of days ago I am migrating a project for a Virtex-5 made in ISE 14.5 to Kintex Ultrascale in Vivado 2019.2. At the moment I have managed to update and adapt almost all the ip cores with the exception of Aurora 8B10B since I cannot generate the same size of the tkeep signal that the previous version has. Could someone tell me how I can configure this to get a 3-bit tkeep?

this is the configuration in Vivado, this generates a tkeep = 8 bits

this is the configuration in ISE, this generates a tkeep = 3 bits

 

[TrickyDicky]

Is it an AXI interface? TKEEP of 3 bits would indicate only a 24 bit data bus. Tkeep 8 bits indicates 64 bits. Possibly they compressed TKEEP (against axi spec) in the ISE version to be a count rather than actual tkeep?

 

[niciki]

Size of TKEEP is the number of bytes computed as:
Number of lanes * Lane Width.

AFAIK ISE 14.5 and IPCore Aurora 8B10B v5.3 generates interface LocalLogic (LL) without TKEEP and Vivado generates AXI interface.

You need a glue logic between them.

 

[Cesar0182]

thanks for your answer @TrickyDicky and @niciki , I just implemented logic to adapt tkeep from 3 bit (Aurora 8B10B v5.3) to 8 bit (Aurora 8B10B v11.1), but I am getting the following errors while synthesizing. Could you explain to me why this happens?

I have been able to verify that those ports are not in l1_coregen_aurora_stub.vhdl.

 

[niciki]

Clean the project and then elaborate the design (not synthesise). Show us errors/warnings at that stage.

 

[Cesar0182]

Clean the project and then elaborate the design (not synthesise). Show us errors/warnings at that stage.

I have not really synthesized the project, the errors I get are when I elaborate it.

 

[niciki]

What are the full config options for Aurora IP core in Vivado? You have only shown the beginning of them. Scroll down and put here all.

 

[Cesar0182]

What are the full config options for Aurora IP core in Vivado? You have only shown the beginning of them. Scroll down and put here all.

@niciki these are all the configuration options

 

[niciki]

Give us the design: HDL or block design to see how you connect the Aurora core.
Are some ports not connected?
Check if you can upgrade Aurora IP (not whole Vivado, just the Aurora IP). AFAIK upgrading this IP Core is free of charge if it is existing - some time ago I had issues with generating and upgrading Aurora IP helped.

One thing - shared logic. Are you make a use of the example design, because shared logic with presented options is in the example design, i.e. not in the core. Try to make them inside the core and eraborate once again.

 

[Cesar0182]

Give us the design: HDL or block design to see how you connect the Aurora core.
Are some ports not connected?
Check if you can upgrade Aurora IP (not whole Vivado, just the Aurora IP). AFAIK upgrading this IP Core is free of charge if it is existing - some time ago I had issues with generating and upgrading Aurora IP helped.

One thing - shared logic. Are you make a use of the example design, because shared logic with presented options is in the example design, i.e. not in the core. Try to make them inside the core and eraborate once again.

I attach the source files and the compressed IP I am using. @niciki I tell you that I have changed to "include shared logic in core" but I am having the same error.

 

[niciki]

Regarding your errors from post #4 - why l1_coregen_aurora_stub.vhdl is in your project?
Delete it from your project and use l1_coregen_aurora_core.v instead as it clearly states that it is a top level module and has your missing ports:

Even better: for generated IP cores in Vivado, Xilinx recommends using .xci files (l1_coregen_aurora.xci in your case). Source: http://www.xilinx.com/support/answers/69690.html

IMHO the best starting point with Aurora is an example design as states in PG046 (Aurora 8B/10B v11.1, LogiCORE IP Product Guide):

 

[Cesar0182]

Regarding your errors from post #4 - why l1_coregen_aurora_stub.vhdl is in your project?
Delete it from your project and use l1_coregen_aurora_core.v instead as it clearly states that it is a top level module and has your missing ports:
View attachment 170783
Even better: for generated IP cores in Vivado, Xilinx recommends using .xci files (l1_coregen_aurora.xci in your case). Source: http://www.xilinx.com/support/answers/69690.html

IMHO the best starting point with Aurora is an example design as states in PG046 (Aurora 8B/10B v11.1, LogiCORE IP Product Guide):
View attachment 170785

thanks for the help @niciki , i was finally able to solve my problem.

 

[niciki]

I am glad that I could help you. What was exactly the solution?