[ModelSim] How to set support to VHDL-2011

[ivlsi]

Hi All,

How can I set support to VHDL-2011 in ModelSim?

Actually I've put the VHDL93 = 2008 line in the modelsim.ini, but it seems it does not catch it. At least, then I try to use an output port in one of the processes, I'm receiving the following error message: "Cannot read output "signal_name"". As far as I know, VHDL-2011 supports using output ports in the processes, but VHDL93 doesn't.

Thank you!

 

[FvM]

Readback of output ports is in fact a VHDL2008 feature, but not supported by all tools. I don't know specifically about Modelsim.

The trivial solution is to declare the port as buffer instead, if you don't want an internal "wire" signal. The previous restriction of requiring buffer ports to be connected to buffer through the hierarchy isn't imposed by any recent tool.