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modelsim error "illegal output port connection"

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samcheetah

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illegal output or inout port connection

i have attatched the verilog code that gives me the error. i have checked this error in the xilinx answers database https://www.xilinx.com/xlnx/xil_ans_display.jsp?getPagePath=11459

it says that i should use named mapping instead of positional mapping when instantiating a module. but i always use named mapping, even though i dont need to. i always write the signals in an instance in the same order as they were declared. so why am i getting this error in modelsim.
 

tkbits

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illegal output port connection

I don't think you want c_in to be an output from module mac.
 

    samcheetah

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samcheetah

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illegal output or inout port connection

c_in is an input to the module but i dont want to watch a change in it because i dont care about it and i will keep it at zero
 

tkbits

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booth algorithm in modelsim

Er, your code...
Code:
// Multiply Accumulate Unit
module mac(out, c_out, a, b, c, d, c_in);

	// Input and output declarations (Interface)
	output [2:0] out;
	output c_out;
	input [2:0] a, b, c, d;
	output c_in;               // <<<<<<-----------

	// Dummy wires (Internals)
	wire [5:0] p1, p2;	

	// Multipliers
	multiplier M1(p1, a, b);
	multiplier M2(p2, c, d);

	// Adder
	cla_add A1(out, c_out, p1[5:3], p2[5:3], c_in);


endmodule
 

    samcheetah

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nand_gates

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illegal output port connection

OK! OK check with the following code .....
This is what tkbit hsa suggested!

Code:
// Testbench
module stimulus();

	reg [2:0] A, B, C, D;
	reg C_IN;

	wire [2:0] OUT;
	wire C_OUT;
	
	mac my_mac ( .out(OUT), .c_out(C_OUT), .a(A), .b(B), .c(C), .d(D), .c_in(C_IN));

	// Set up the monitoring for the signal values
	initial
	begin
  	$monitor($time," A= %d, B=%d, C=%d, D=%d, --- C_OUT= %d, OUT= %d\n",
					A, B, C, D, C_OUT, OUT);
	end

	// Stimulate inputs
	initial
	begin
		C_IN = 1'b0;
	
		A = 4'd1; B = 4'd1; C = 4'd1; D = 4'd1; 

		#5 A = 4'd2; B = 4'd1; C = 4'd1; D = 4'd2;

		#5 A = 4'd1; B = 4'd1; C = 4'd2; D = 4'd1; 

		#5 A = 4'd2; B = 4'd2; C = 4'd2; D = 4'd2; 
  end

endmodule

// Multiply Accumulate Unit
module mac(out, c_out, a, b, c, d, c_in);

	// Input and output declarations (Interface)
	output [2:0] out;
	output c_out;
	input [2:0] a, b, c, d;
	input c_in;

	// Dummy wires (Internals)
	wire [5:0] p1, p2;	

	// Multipliers
	multiplier M1(p1, a, b);
	multiplier M2(p2, c, d);

	// Adder
	cla_add A1(out, c_out, p1[5:3], p2[5:3], c_in);


endmodule

// 3-bit Multiplier
module multiplier(p, a, b);

	// Input and output declarations (Interface)	
	output [5:0] p;
	input [2:0] a, b;

	// Dummy wires (Internals)
	wire a1b0, a2b0, c10, c11, c20, c21, s11, s12;

	// Instantiate gate logic gate primitives
	and (p[0], a[0], b[0]);
	and (a1b0, a[1], b[0]);
	and (a2b0, a[2], b[0]);

	// Instantiate units with half adders
	basic_cell_halfadd bc_ha1(p[1], c10, a[0], b[1], a1b0);
	basic_cell_halfadd bc_ha2(p[2], c20, a[0], b[2], s11);
	basic_cell_halfadd bc_ha3(s12, c12, a[2], b[1], c11);

	// Instantiate units with full adders
	basic_cell_fulladd bc_fa1(s11, c11, a[1], b[1], a2b0, c10);
	basic_cell_fulladd bc_fa2(p[3], c21, a[1], b[2], s12, c20);
	basic_cell_fulladd bc_fa3(p[4], p[5], a[2], b[2], c12, c21);
	
endmodule

// Basic cell of the multiplication unit with full adder
module basic_cell_fulladd(sum_out, c_out, a, b, sum_in, c_in);
	
	// Input and output declarations (Interface)	
	output sum_out, c_out;
	input a, b, sum_in, c_in;

	//Dummy wires (Internals)
	wire ab;

	and (ab, a, b);	

	fulladd FA(sum_out, c_out, ab, sum_in, c_in);

endmodule

// Basic cell of the multiplication unit with half adder
module basic_cell_halfadd(sum_out, c_out, a, b, sum_in);
	
	// Input and output declarations (Interface)	
	output sum_out, c_out;
	input a, b, sum_in;

	//Dummy wires (Internals)
	wire ab;

	and (ab, a, b);	

	halfadd HA(sum_out, c_out, ab, sum_in);

endmodule

// 3-bit Carry Lookahead Adder
module cla_add(sum, c_out, a, b, c_in);

	// Input and output declarations (Interface)
	output [2:0] sum;
	output c_out;
	input [2:0] a,b;
	input c_in;

	// Dummy wires (Internals)
	wire p0,g0, p1,g1, p2,g2;
	wire c1, c2, c3;
	wire d1, d2, d3, d4, d5, d6;

	// computation of the carry propagated for each stage
	xor (p0,a[0],b[0]);
	xor (p1,a[1],b[1]);
	xor (p2,a[2],b[2]);
	
	// computation of the carry generated for each stage
	and (g0,a[0],b[0]);
	and (g1,a[1],b[1]);
	and (g2,a[2],b[2]);
	
	// computation of the carry for each stage
	and (d1,p0,c_in);
	or (c1,g0,d1);

	and (d2,p1,g0);
	and (d3,p1,p0,c_in);
	or (c2,g1,d2,d3);

	and (d4,p2,g1);
	and (d5,p2,p1,g0);
	and (d6,p2,p1,p0,c_in);
	or (c3,g2,d4,d5,d6);

	// computation of the sum
	xor (sum[0],p0,c_in);
	xor (sum[1],p1,c1);
	xor (sum[2],p2,c2);
	
	// Assign carry output
	assign c_out = c3;

endmodule

// 1-bit Full Adder
module fulladd(sum, c_out, a, b, c_in);

	// I/O port declarations
	output sum, c_out;
	input a, b, c_in;

	// Internal nets
	wire s1, c1, c2;

	// Instantiate logic gate primitives
	xor (s1, a, b);
	and (c1, a, b);

	xor (sum, s1, c_in);
	and (c2, s1, c_in);

	xor (c_out, c2, c1);

endmodule

// 1-bit Half Adder
module halfadd(sum, c_out, a, b);

	// I/O port declarations
	output sum, c_out;
	input a, b;

	// Instantiate logic gate primitives
	xor (sum, a, b);
	and (c_out, a, b);

endmodule
 

echo47

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illegal output port connection in verilog

Yes, you tried to connect a module output to a register, and that's not allowed.

If you intend to target a Xilinx device, I'm curious why you are using low-level gate arithmetic. Perhaps this is a learning exercise.
 

    samcheetah

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samcheetah

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llegal output or inout port connection

oh, such a stupid mistake. thanx guyz

well echo47, the reason im using a gate-level multiplier is that a friend of mine asked me to do this. actually he has to implement turbo codes in an FPGA and he says that space is not a consideration but speed is. so he wants the fastest multiplier, and he needs lots of them! i told him that behavioral multipliers are fast too (booth's algorithm etc) but he doesnt like the idea.

so im just doing what he wants me to do.

and tkbits, thanx again for pointing out my mistake. and im sorry i didnt understand what you said
 

echo47

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illegal output or inout port connection (port

I would try using ordinary Verilog arithmetic, and then see how well the compiler/optimizer works.
It's a lot easier to write something like "out = a * b + c * d + cy".
 

    samcheetah

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samcheetah

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modelsim inout

ive seen that. actually when you write something like a*b it is inferred as a MULT 18x18 in spartan 3. and lets say that you have the spartan 3 starter kit with an XC3S200 with 12 multipliers, you would only be able to implement 6 such multiply-accumulate blocks. and even though you need to multiply two 3 bit numbers, the whole 18 bit multiplier is utilized.

so if someone wants 512 such units and nothing else then i thought that such an approach would be better.

please give your comments
 

echo47

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illegal output port connection (1st connection).

Set the MULT_STYLE constraint to LUT to force ISE to implement distributed multipliers.

When I implement your gate-level code on a Spartan-3, I get about 129 MHz speed.
When I use an equivalent Verilog arithmetic expression, I get a slightly smaller layout that runs about 145 MHz.
I used default routing effort, nothing fancy.
ISE automatically selected distributed multipliers without my using MULT_SYTLE.
The ISE optimizer is usually pretty smart.

Here's my top module. It uses a counter to generate all combinations of a,b,c,d,cin for test purposes. It computes both multiplier methods simultaneously, but you can comment-out one of the two lines marked "optional" to do a speed test of only one method:
Code:
module top (clk, cout0, out0, cout1, out1);
  input                 clk;        // synthesis attribute PERIOD clk 6ns;
  reg             [2:0] a=0, b=0, c=0, d=0;
  reg                   cin=0;
  wire            [2:0] mout;
  wire                  mcout;
  output reg            cout0, cout1;
  output reg      [2:0] out0, out1;

  mac mac1 (.out(mout), .c_out(mcout), .a(a), .b(b), .c(c), .d(d), .c_in(cin));

  always @ (posedge clk) begin
    {d,c,b,a,cin} <= {d,c,b,a,cin} + 1;
    {cout0,out0} <= {mcout,mout};  // optional
    {cout1,out1} <= ((0 + a * b) >> 3) + ((0 + c * d) >> 3) + cin;  // optional
  end
endmodule
I don't know the goal of your (friend's) arithmetic, but it seems unusual (wrong?) to discard the least-significant product bits before adding.

You aren't going to fit 512 of those things into an XC3S200. Maybe you are planning a bigger chip.

This Xilinx app note describes a tricky method to implement two small multipliers in one 18x18 block multiplier. Of course that only buys you a factor of two.
https://direct.xilinx.com/bvdocs/appnotes/xapp467.pdf

Your first message has a long link that makes all our messages really wide. You could edit it and substitute this link:
https://www.xilinx.com/xlnx/xil_ans_display.jsp?getPagePath=11459
 

    samcheetah

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samcheetah

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illegal output port connection (5th connection)

what version of XST are you using? i have 6.2i

if you are using 8.1i then can you give me the synthesis report because im getting somewhat different results.
 

echo47

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modelsim real multiply

Oops, I forgot to mention ... yes I'm using ISE 8.1.01i. Device 3s200-4-ft256. I'm not sure what will happen with ISE 6.2i. Typically, 8.1i gives faster performance than 6.x and 7.x.

I just now tried it with ISE 6.3.03i (and Virtex-II because I don't have Spartan-3 installed in that version), and it defaulted to using block multipliers, so I had to attach an attribute to the module:
// synthesis attribute MULT_STYLE top LUT

Using your method, the speed was similar between 6.3.03i and 8.1.01i (both 170 MHz).
Using my method, the speed was much worse in 6.3.03i than 8.1.01i (115 MHz and 170 MHz).
That doesn't surprise me, because 8.1 has a better optimizer than 6.3.
I'm still using default routing effort. Remember these are Virtex-II numbers.

Here's my full project build report using Spartan-3 in 8.1.01i. Synthesis info is near the top. I commented-out that first optional line (your method), so it only compiled the second optional line (my method).
 

    samcheetah

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eslama

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Re: modelsim error "illegal output port connection&quot

I also have the same error but in different code.
plz,check this code to me
 

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