samcheetah
Advanced Member level 2

illegal output or inout port connection
i have attatched the verilog code that gives me the error. i have checked this error in the xilinx answers database **broken link removed**
it says that i should use named mapping instead of positional mapping when instantiating a module. but i always use named mapping, even though i dont need to. i always write the signals in an instance in the same order as they were declared. so why am i getting this error in modelsim.
i have attatched the verilog code that gives me the error. i have checked this error in the xilinx answers database **broken link removed**
it says that i should use named mapping instead of positional mapping when instantiating a module. but i always use named mapping, even though i dont need to. i always write the signals in an instance in the same order as they were declared. so why am i getting this error in modelsim.