Modelsim do not provide output for module with delay more then 1ns
I'm trying to delay ripple clock where output of D-flipflop will go through a delay cell before reaching another D-flipflop. If I use delay cell with 1ns delay, Modelsim simulate it fine.
Re: Modelsim do not provide output for module with delay more then 1ns
Why pulse duration have to be larger then Delay ? suppose I want to give a 1ns pule at one node and want to send the same pulse at different node with with 2n delay, it is physically possible to design a 2ns delay block manually. Now I wanna use that block as module to simulate Verilog, what should I do ?
Re: Modelsim do not provide output for module with delay more then 1ns
The continuous assign statement and gate primitives simulate using an inertial delay model. That means the output cannot change faster than the input. You want a transport delay model. For that you need to use specify block path delays, or the non-blocking assignment. Specify blocks can get quite involved, so I'll just show the non-blocking assignment version:
Code Verilog - [expand]
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`timescale1ns/10psmodule CLKDLY2X1(inputwire A,outputreg Z);always@A Z <=#2 A;endmodule