dragonfury
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Hello,
I have a confusion regarding modelling a DDR3 UDIMM (unbuffered DIMM) with dual rank (two ranks). The question is,
Are the clock and data signal transmission lines separate for both ranks of the UDIMM or the transmission lines on one side is connected through vias to the other side of the DIMM?. I am asking this question because I am unclear about the electrical loading the UDIMM creates on the memory controller. Hence, if the two ranks on a UDIMM are independent, it would seem that the two ranks are two separate loads on the UDIMM, rather than a single load.
I would be grateful for a prompt reply.
I have a confusion regarding modelling a DDR3 UDIMM (unbuffered DIMM) with dual rank (two ranks). The question is,
Are the clock and data signal transmission lines separate for both ranks of the UDIMM or the transmission lines on one side is connected through vias to the other side of the DIMM?. I am asking this question because I am unclear about the electrical loading the UDIMM creates on the memory controller. Hence, if the two ranks on a UDIMM are independent, it would seem that the two ranks are two separate loads on the UDIMM, rather than a single load.
I would be grateful for a prompt reply.
