Modeling VCO load effect on PLL settling

[itacool]

Hello,
I have a PLL where the VCO's load is abruptly changing.
I want to model the load variation as a small perturbation assuming linear system for calculating the loop response. any book chapter/paper deals with that?

Thanks

 

[KlausST]

Hi,

The VCO output is a digital logic level clock signal.
If you load it in a way that the signal current is increased ... it won't affect the VCO frequency significantly.

Thus it won't affect the PLL loop.

Klaus

 

[itacool]

Hi,
The VCO is a cross coupled LC . The PLL loop may not lose locking, but i want to calculate the transient behavior till settling.
The load is abruptly change (like step response).

Thanks

 

[ZoOneR]

Hi,
In RF Microelectronics written by Razavi, in chapter 10, there is a section on Settling Behaviour, maybe it helps.

 

[BigBoss]

It's pretty difficult to calculate transient behavior of a PLL. Abruptly changes in load will result to Frequency Pulling ( Frequency Shift ) in frequency domain and it will also create an extra Phase Noise due to this immediate frequency shift.If behavioral models are available, a transient simulation can be done with a variable load but it will not guarantee to provide the exact response of the PLL.

 

[pancho_hideboo]

I have a PLL where the VCO's load is abruptly changing.
I want to model the load variation
as a small perturbation assuming linear system
for calculating the loop response.

What do you want to mean by "linear system" ?

Do you mean phase domain model of PLL ?

If so, load pulling effect of VCO is equivalent to step shift of reference.
We can use phase domain model of PLL in not only AC analysis but also Transient analysis.

Evaluate load pulling effect of free running VCO, Kvco and Kpfd.
Then estimate step shift of reference by these value.

You can evaluate frequency settling behavior of PLL.

it will also create an extra Phase Noise due to this immediate frequency shift.If behavioral models are available,

We can not evaluate this by phase domain model of PLL.

 

[pancho_hideboo]

If so, load pulling effect of VCO is equivalent to step shift of reference.

Forget this.

Pertubation of reference is in band of PLL Loop Bandwidth.

Add step shift to output of VCO.

 

[itacool]

Hello and thanks for all replies.
I meant linear system as assuming the loop is near locking and can be modeled using phase variables. The perturbation is small that the loop is still stable. Let say the load is changing from Z1 to Z2, how to model it in the phase variables. I thought also that it acts as a step phase in output, but not sure how to transform the impedance ratio to step amount.

Thanks!

 

[pancho_hideboo]

I meant linear system as assuming the loop is near locking
and can be modeled using phase variables.

Output is a phase not frequecny in phase domain PLL model.

Let say the load is changing from Z1 to Z2,
how to model it in the phase variables.

Evaluate Kvco and frequceny for Z1 and Z2 of VCO.

I thought also that it acts as a step phase in output,
but not sure how to transform the impedance ratio to step amount.

f1 for Z1.
f2 for Z2.

(f2-f1)/Kvco.
Add this value as step pulse in front of VCO input.

 

[itacool]

Do you mean that (f2-f1)/Kvco is the voltage step in tuning voltage of the VCO ? (has unit of volts,not rad)

Thanks

 

[pancho_hideboo]

Do you mean that (f2-f1)/Kvco is the voltage step in tuning voltage of the VCO ? (has unit of volts,not rad)

Yes.......