Modeling Simple ADC / DAC in VHDL

[wenglao]

simple adc vhdl

anyone can teach me how ??

 

[avimit]

adc dac vhdl

ADC: take a file with voltage or current values in it, yes a text file. These are your analog values. Then write a vhdl model which will read this file. VHDL has a datatype called 'real' you will be able to read values from file, into a variable which is of type 'real'.
By reading these values you are effectively 'sampling' your analog value. So the frequency at which you will read will be your 'sampling freq'. So txt values in your files must correspond to that 'sampling freq'
now convert this 'real' type into std_logic_vector, and output it.
Thats it.
do the reverse for DAC.
Kr,
Avi
http://www.vlsiip.com