TKruger
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Hi Guys
My name is Tiaan, and i just signed up to this forum.
Im currently designing a system in VHDL, and using a MAX7000S CPLD from Altera.
I, However am experiencing a bit of a problem with my counter. It starts at 0 and counts up to 9 and is supposed to reset.
I have included the code and the error.
Can anyone please give me a hint, or correct me where im going wrong.
Thanking in advance.
My name is Tiaan, and i just signed up to this forum.
Im currently designing a system in VHDL, and using a MAX7000S CPLD from Altera.
I, However am experiencing a bit of a problem with my counter. It starts at 0 and counts up to 9 and is supposed to reset.
I have included the code and the error.
Can anyone please give me a hint, or correct me where im going wrong.
Thanking in advance.