MOD-9 Counter in VHDL

[TKruger]

Hi Guys
My name is Tiaan, and i just signed up to this forum.

Im currently designing a system in VHDL, and using a MAX7000S CPLD from Altera.
I, However am experiencing a bit of a problem with my counter. It starts at 0 and counts up to 9 and is supposed to reset.
I have included the code and the error.

Can anyone please give me a hint, or correct me where im going wrong.
Thanking in advance.

 

[lucbra]

couple of issues

in the others case you are giving reset a value (reset is an input, not an output)
buffer is not intended for integers
if you want to read the value back, make a construct with a temp signal