ML410 Virtex-4 development board DDR (SDRAM) interface

[mjuneja]

For one of my application, I need to develop interface with DDR chips provided on the ML-410 board.

But as most of the control lines going to both these chips from FPGA are common, only dq, dqs and dm are separate.

So my doubt is do we need to develop a common DDR controller to interface with both these chips.

If yes, then how to de-multiplex common controller lines to different FPGA pins especially the bi-directional lines viz. dq & dqs.

I tried (in VHDL)

      cntrl0_ddr_dqs(3 downto 2) <= cntrl0_ddr_dqs1 when dec = '0' else (others => 'Z');
		cntrl0_ddr_dqs(1 downto 0) <= cntrl0_ddr_dqs1 when dec = '1' else (others => 'Z');
		cntrl0_ddr_dm(1 downto 0)   <= cntrl0_ddr_dm1 when dec = '1' else (others => 'Z');
		cntrl0_ddr_dq(15 downto 0)  <= cntrl0_ddr_dq1 when dec = '1' else (others => 'Z');  	
		cntrl0_ddr_dm(3 downto 2)   <= cntrl0_ddr_dm1 when dec = '0' else (others => 'Z');
		cntrl0_ddr_dq(31 downto 16) <= cntrl0_ddr_dq1 when dec = '0' else (others => 'Z');

where cntrl0_ddr_dqs, cntrl0_ddr_dq & cntrl0_ddr_dm are the lines defined in the top module entity port and cntrl0_ddr_dqs1, cntrl0_ddr_dq1 & cntrl0_ddr_dm1 are the lines from the common DDR controller designed.

But I am getting the below error during translate.

ERROR:NgdBuild:924 - bidirect pad net 'DDR/cntrl0_ddr_dq1<0>' is driving
non-buffer primitives:
.
.
.
ERROR:NgdBuild:924 - bidirect pad net 'DDR/cntrl0_ddr_dq1<15>' is driving
non-buffer primitives:
ERROR:NgdBuild:924 - bidirect pad net 'DDR/cntrl0_ddr_dqs1<0>' is driving
non-buffer primitives:
ERROR:NgdBuild:924 - bidirect pad net 'DDR/cntrl0_ddr_dqs1<1>' is driving
non-buffer primitives:

What can be the probable cause of error, do i need to change the way I have de-multiplexed the common lines or some property I need to change in Synthesis, translate steps.

Thanks

 

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You didn't supply enough of the code to allow someone to answer. If you are using the DDR controller from Xilinx then the I/O primitives are already inside the controller code. You can't add some multiplexers outside the DDR IP core without getting errors just like you are getting. What you would be doing is adding logic between the I/O primitive (e.g. IOBUF) and the package pins.

If you have a common set of control lines and different sets of DQS, DQ, and DM you need to select a compatible memory device that has that type of pinout and modify it if necessary. Though I'm surprised you can't just start with a core generated for the base ML410 board (generating the core based on a specific development board) and modify it instead of trying to come up with your own configuration of the IP for the ML410 board.