mixer output DC offset

[chacha]

hi experts,

iam designing a folded mixer for a low IF reciever.
iam getting a huge DC offset voltage at the output (around 720mv).

how can i reduce this offset voltage??

i GUESS Khouly can answer it...

 

[noiseless]

DC offset?

should be DC common mode voltage

 

[khouly]

i can say like noiseless , it may be ur dc bais coponent

let me say how DC offset generated , and how it affect the ZIF receiver "zero IF"

when the lo leackage go from the mixer to the LNA , it attenuated due port to port isolation in LNA , and mixer , then it is go through the antenna
and received again , amplified by LNA , and now will be mixed in mixer with the same LO , so it will generate the DC offset , this appers in the ZIF receivers

khouly

 

[chacha]

khlouly explained it very well......
but how can we reduce this LO to RF leakage??

Added after 24 seconds:

khlouly explained it very well......
but how can we reduce this LO to RF leakage??

Added after 7 minutes:

khlouly explained it very well......
but how can we reduce this LO to RF leakage??

 

[khouly]

mainly if ur using a gilbert cell mixer , it's LO to RF leakage is very good , the main
and if ur LNA is cascode , it also will reduce the LO leakage

khouly

 

[manissri]

can kouly explain.,.
the carrier leakage in PA in trasmitter side ..
it would be much helpful..
manish'

 

[khouly]

if the upconversion mixer have a feed through then the output of the mixer will have the carrier frequency un modulated , then

in reciver this component will appear as DC offset
but this may not ahppen coz the TX freq is different fromRX

and that's why there is duplexer at the anteena

khouly

 

[Youncen]

if dc offset can be reduced by subharmonic mixer configuration at the cost of gain.......

 

[OMEsystem]

hi experts,

iam designing a folded mixer for a low IF reciever.
iam getting a huge DC offset voltage at the output (around 720mv).

how can i reduce this offset voltage??

i GUESS Khouly can answer it...

1)
do you insert ac coupling cap preceded your switching stage in folded structure?
or just dc coupling? would you upload your circuit so that we can analyze it in
more detail.
2)
If the reason is because of the LO feedthrough, you can check the LO power at
LNA input to see how large it is? 720mV looks too large for me.