Most simulators now support mixed mode simultaion.
You can instantiate a VHDL module inside verilog or vice versa . When compling the design make sure you compile it in the right order. i,e, if VHDL module is an instance in verilog , compile all your vhdl files and then your verilog files. After that just compile as usaul.
Use mixed language simulators, for example synopsys has a tool by name VCS MX in which codes of both verilog and VHDL can be compiled and sumulated together (refer its pdfs for the commands)