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You can mix, the tools will take care of it for you without any issues. Implementation is not the issue, but QoR might be.
The only concern is that you might be creating insertion delays that are very pessimistic when the worst case corner of each Vt is considered. The way process variation affects the low Vt cells is different from the way it will affect the high Vt cells. Some of it is random, but some of it is systematic and that would mess with your clock tree balancing. You could create a scenario where your actual silicon has lowVt cells that are consistently 5% slower than typ lowVt, and highVt cells that are 5% faster than typ highVt(just an example). Had you used cells of the same Vt all over, you could be eliminating the systematic variation component.
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