Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Mismatch Parameters for 65nm TSMC technology

PhdSA

Newbie
Joined
Mar 18, 2024
Messages
1
Helped
0
Reputation
0
Reaction score
0
Trophy points
1
Activity points
16
Hello,

I am designing a current steering DAC based on technology TSMC 65 nm. I have a technology 65 nm CMOS TSMC in cadence. I asked how can i extract the mismatch technology parameters Avth and Aβ from this technology. I'm so gratefull if someone have these parameter send me a document.
1710837495150.png



Best Regards
 
If you're a legit user then that info should be in PDK
docs and model params.

If you're not then I would suggest using what you may
find in "open" kits on the Web (believe I've seen -some-
65nm, forget where).
 

LaTeX Commands Quick-Menu:

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top