Minimum NDIFF to HOT_NTUB spacing Design Rule

[malizevzek]

ndiff to hot_ntub

What's behind this Design Rule? What happens if NDIFF is too close to Hot NTUB?

 

[Colbhaidh]

minimum ndiff to hot_ntub

Consider that the NDiff will move with each temperature process in the FAB.
So the most important thing is to consider any PMOS in (N Diff) could become close to an PWell biased at 0 Volts. Worst case, the N Diff would be at the Vcc supply to the pmos transistors.
Given that the N-Diff will diffuse with temperature and in this case towards the P -Diff then worst case the supply voltage on the N Diff will get really close to the ground voltage Vss on the P-Diff.
This could lead to leakage between supply and ground. It may only create leakage when say an invertor was energised and so the leakeage becomes dynamic.

 

[malizevzek]

hot_ntub

I didn't quite understand your answer.

So the most important thing is to consider any PMOS in (N Diff) could become close to an PWell biased at 0 Volts. Worst case, the N Diff would be at the Vcc supply to the pmos transistors.

Isn't the whole PMOS (I mean N-tub) buried in P-substrate anyway? In the case when N-tub is Vcc biased, and P-substrate ground biased, that is the usual situation, isn it?

To make things clear - I get the error for the distance between source N Diff of NMOS transistor and N-TUB of neighboring PMOS transistor.
As far as I understod, hot N-tub is the one that is not connected to VCC. I fail to understand what's different if the case of hot N-tub

 

[Colbhaidh]

minimum diff to hot_ntub

Yes. The pmos is completely surrounded by an N-Well tub which is biased at Vcc or some other voltage. (Can even be floating in some 5V tolerant IOs on 1.8V cmos). If this N-Well edge on the surface comes to close to an unrelated N+ of an nmos transistor then the P- substrate isolating the two diffusions may become insufficient. If the minimum distance in the design rules is violated, then although the layout may appear OK, fabrication variables like registration (misalign between the NWell layer and the S/D layers and also sideways diffusion for within specified temperature limits for all the anneals). So the separation of the NWell to unrelated N+ becomes small enough that there is no real P- isolation from the substrate at the surface. This can cause leakage.
Also consider unrelated metal 1 running across the isolation the separates the NWell from the unrelated N+. This isolation may be thick, but you still have an nmos transistor where the metal over isolation acts as a gate, the P- substrate acts as the channel and the NWell and unrelated N+ acts as source and drains.
There could be sufficient coupling from voltages on the metal 1 to induce a weak inversion in the P-substrate separating these two N+ regions.

 

[malizevzek]

ndiff in cmos

OK, thanks, that part is clear.
One more question - what difference does it make if the NTUB is hot or not, that is, why do we have different design rules then (I mean this Minimum NDIFF to NTUB/HOT_NTUB Spacing)

 

[daniba]

Hi, everyone,
I would like to know the answer, too.
For example, if i have two different supply voltages, i consider both voltages as being cold, or one of them is hot?
Can it be related to hot carriers from substrate ?