This is quite typical for foundries (there are exceptions of course).
What they tell you is - "use SPICE models for pre-characterized capacitors for several fixed sizes, don't use parasitic extraction tools, and don't use capacitors with sizes different from what we measured".
And they are probably right, as in that most of the parasitic extraction tools (based on pattern matching, or rule based method) the 3D capacitive effects are not handled accurately and rigorously.
The problem is that ITF (or iRCX, ICT, ...) is all what you get, even if you try to run full wave electromagnetic field solvers.
And also - there are many situations where you have to use capacitors with sizes different from what foundry recommends you.
What I am doing when using a 3D accurate capacitance extraction tools (like F3D), is a kind of reverse engineer the MIM stack, either guessing or getting information on - dielectric thickness and diel. constant for the MIM dielectric, top metal thickness, etc. Then, you can use parasitic extraction to calculate capacitances for the whole circuit - considering MIM or MOM capacitors as parts of the interconnects. This way, both the absolute value of the capacitors, as well as all the parasitic elements are taken into consideration. Remember parasitics, even very small ones, are detrimental for precision analog circuits requiring precise capacitor matching or weighting.
This is not correct. ITF (or similar format) file is supposed to be a complete description of the BEOL stack for any applications - digital, analog, image sensors, power management, etc.