[SOLVED] MIMCAP CTM and CBM information

[mh_akbarpour]

Hi All,
I am designing an amplifier using TSMC65nm. The available MIMCAP models are valid up to 30GHz and I need to verify them at 60GHz. so I need to simulate them at 60GHz.
I need to know the physical distance of CTM and CBM metal layers used in MIMCAP from other layers.
Does anybody know where to find these information?
What about the dielectric constant used in between CTM and CBM?

Thanks all

 

[dgnani]

look at the vertical profile in Calibre parasitic extraction rules or in the ITF files used for generating digital timing info

 

[mh_akbarpour]

Thanks dgnani,
I looked at Calibre parasitic extraction rules but there was not information about the CTM and CBM.
I found it in one of the documents from the kit. T-N65-CM-SP-006() has the layer stack including these layers(unlike any other document).

 

[dgnani]

Thanks dgnani,
I looked at Calibre parasitic extraction rules but there was not information about the CTM and CBM.
I found it in one of the documents from the kit. T-N65-CM-SP-006() has the layer stack including these layers(unlike any other document).

sorry mh_akbarpour, I had not double-checked the docs, those are the usual places where I get that info.

The fact that that info is not in the PEX rules is actually very troubling as it means that the RC extraction rules available for mixed-mode are not complete. I guess we'll have to ask TSMC what that is about.

The ITF was probably a bad place to look into as it usually only concern itself with layers used in the digital process

The document you found is for G+ flavor correct? I had for no apparent reason assumed you were working with LP...

I did not look at more than the title page, I will see if there is anything about LP stacks in there (which we are using)

 

[mh_akbarpour]

dgnani,
You are right, I use G+ process for my design. The reason I didn't find the information I needed was that I used to use T-N65-CM-SP-018 which is a complete guide for the models provided by the design kit. In this document, Chapter 9 discuss the interconnect model thoroughly but does not include CTM and CBM. I assumed that if I can't find it here, then there is no other document having the information I need.
Anyway, thanks again for your comments. I found other valuable information from those files and rules you mentioned.

 

[timof]

sorry mh_akbarpour, I had not double-checked the docs, those are the usual places where I get that info.

The fact that that info is not in the PEX rules is actually very troubling as it means that the RC extraction rules available for mixed-mode are not complete. I guess we'll have to ask TSMC what that is about.

This is quite typical for foundries (there are exceptions of course).
What they tell you is - "use SPICE models for pre-characterized capacitors for several fixed sizes, don't use parasitic extraction tools, and don't use capacitors with sizes different from what we measured".
And they are probably right, as in that most of the parasitic extraction tools (based on pattern matching, or rule based method) the 3D capacitive effects are not handled accurately and rigorously.
The problem is that ITF (or iRCX, ICT, ...) is all what you get, even if you try to run full wave electromagnetic field solvers.
And also - there are many situations where you have to use capacitors with sizes different from what foundry recommends you.

What I am doing when using a 3D accurate capacitance extraction tools (like F3D), is a kind of reverse engineer the MIM stack, either guessing or getting information on - dielectric thickness and diel. constant for the MIM dielectric, top metal thickness, etc. Then, you can use parasitic extraction to calculate capacitances for the whole circuit - considering MIM or MOM capacitors as parts of the interconnects. This way, both the absolute value of the capacitors, as well as all the parasitic elements are taken into consideration. Remember parasitics, even very small ones, are detrimental for precision analog circuits requiring precise capacitor matching or weighting.

The ITF was probably a bad place to look into as it usually only concern itself with layers used in the digital process

This is not correct. ITF (or similar format) file is supposed to be a complete description of the BEOL stack for any applications - digital, analog, image sensors, power management, etc.

 

[dgnani]

This is quite typical for foundries (there are exceptions of course).
What they tell you is - "use SPICE models for pre-characterized capacitors for several fixed sizes, don't use parasitic extraction tools, and don't use capacitors with sizes different from what we measured".
And they are probably right, as in that most of the parasitic extraction tools (based on pattern matching, or rule based method) the 3D capacitive effects are not handled accurately and rigorously.
The problem is that ITF (or iRCX, ICT, ...) is all what you get, even if you try to run full wave electromagnetic field solvers.
And also - there are many situations where you have to use capacitors with sizes different from what foundry recommends you.

What I am doing when using a 3D accurate capacitance extraction tools (like F3D), is a kind of reverse engineer the MIM stack, either guessing or getting information on - dielectric thickness and diel. constant for the MIM dielectric, top metal thickness, etc. Then, you can use parasitic extraction to calculate capacitances for the whole circuit - considering MIM or MOM capacitors as parts of the interconnects. This way, both the absolute value of the capacitors, as well as all the parasitic elements are taken into consideration. Remember parasitics, even very small ones, are detrimental for precision analog circuits requiring precise capacitor matching or weighting.



This is not correct. ITF (or similar format) file is supposed to be a complete description of the BEOL stack for any applications - digital, analog, image sensors, power management, etc.

mimcap in tsmc are not in fixed size steps, they come in a fully characterized pcell. Nobody expects them to be extracted as parasitics but the lack of parasitic to the metal in the pcell could be problematic. In addition mimcaps in TSMC are thin oxide devices so using stack info for an analog device has very strong limitations as you won't be able e.g. to characterize mismatch nor their process variation as you do not have correlation data. Having one of the new 3D solvers coming to the market would not hurt but the price is still too steep for us.

There are many examples of processes where the digital runs do not have access to analog-devices such as mimcap, e.g. tsmc25, I have not checked for tsmc65 but the fact that mimcap layers are absent from their ITFs might be a good indication

 

[timof]

I suppose that "full characterization" does not include parasitics (layout dependent) - right?
Also, if you need to use MIM cap with a width smaller than the design rule minimum width(think of image sensors with pixel pitch limitation, for example) - SPICE models do not support that.

For narrow MIM capacitors, the SPICE model is not valid (the periphery component of the capacitor is changed by the surrounding metallization).

I am talking not about the microscopic (device-to-device) mismatch, but about systematic mismatch caused by the layout.

MIM stack info can be included into the ITF file and used for precise parasitic capacitance extraction.

If the cost of failed chips and lost time to market is lower than the cost of the software tool license - then yes, it's more cost efficient to use a trial-and-error method, as opposed to extraction/simulation.

 

[dgnani]

I suppose that "full characterization" does not include parasitics (layout dependent) - right?

that is what I wrote, right?

Also, if you need to use MIM cap with a width smaller than the design rule minimum width(think of image sensors with pixel pitch limitation, for example) - SPICE models do not support that.

For narrow MIM capacitors, the SPICE model is not valid (the periphery component of the capacitor is changed by the surrounding metallization).

I am talking not about the microscopic (device-to-device) mismatch, but about systematic mismatch caused by the layout.

that would be a nice application e.g. if your signal gain depends on the absolute value of a single cap (charge amp); my observation (which you replied to) though was about the PDK mimcap's within their range of characterization and the fact that PEX file missing mimcap metal profile was compromising accuracy; if CTM/CBM were present in the calibration data the parasitic extraction would be perfectly adequate (below microwave frequencies at least)

MIM stack info can be included into the ITF file and used for precise parasitic capacitance extraction.

it sure can but in many cases it is not

If the cost of failed chips and lost time to market is lower than the cost of the software tool license - then yes, it's more cost efficient to use a trial-and-error method, as opposed to extraction/simulation.

We have successfully fabricated mimcap-based, low-noise, 13-bit ADCs that worked on first silicon; same for pixel sensors that relied on ILD caps (you just need to trim).
There are definitely gains to be made by having a more accurate cap extraction tool but one can design around it in most cases.
Consider also that there is a limitation on increasing accuracy of extraction because of (random) mismatch/variations: there is little to gain once the accuracy on your extraction on typical process is much smaller than the process random variations (on-chip or run-to-run).

 

[Intel_Inside]

Hello Guys

I am very happy to find this thread on the TSMC 65nm PDK. sorry to be little out of topic though.
I had to design some spiral inductors with this technology at 24 GHz.
I am a complete newbie in this field and have never designed an inductor before.
Could someone tell me which tool could I use to generate the layout of my inductors first? Will Cadence VPCD + Sonnet be a good combination.?
Has anyone already created a .matl file (substrate file) for sonnet using this technology for the layer stack with the UTM ? could you please share it with me so that i could cross check mine?
Any other suggestions to use a different tool is welcome. as i said I am just beginning

Also there are thousands of abbreviations used in the pdk which are not defined in the same document. could someone tell me whether there exists any document with all abbreviations defined?

thanks a lot

AB