You're misinterpreting the statement.
address/data bits clocked in on positive edge....i.e. they were clocked out (master device) on the falling edge and sampled (microchip) on the rising edge
data bits are clocked out on the positive edge...i.e. the bits are clocked out (microchip) on the rising edge and sampled (master device) on the falling edge
btw. this is not a SPI interface, so I don't expect it to be compatible with mode 0, which it doesn't look like it is, but the description is consistent with the drawing.