Hello, I'm using Microsemi Libero Soc v11.8 to develop VHDL code for an IGLOO nano FPGA.
The problem I have, is that for a certain net the tool automatically adds an input clock buffer and I am not allowed to allocate the net to the pin I want, only to global clock pins.
How can I disable this? In Xilinx there was a constraint "clock_dedicated_route = false", is there something similar in microsemi's tool?
Thank you.
The only reasons it would promote a pin to a clock buffer is if it was heavily loaded or is used as a clock.
You might be able to instantiate a regular input buffer in the code and the global buffer, so it can't promote anything as you've already instantiated the correct primitives you wanted.