Hi slutarius,
Following the LogiCORE IP MicroBlaze Micro Controller System v2.2, PG116 April 2, 2014, I have understood that merging the .elf file with the design is only possible after the Synthesiz Project' stage. See the flowchart on page 30, Figure 4-9: Generic Vivado Tool Flow.
This comes as a surprise to me!
I thought it would be possible somehow populate the BRAMs of a uBlaze MCS with an .elf and then run the entire design in simulation. This make debugging easy. I don't understand why Xilinx would allow to do such a thing.
Nevertheless I have opened a thread in the Xilinx forums and will wait to see their response.