Merging NWELLs of Thick Oxide gate transistor

[dinesh hegde]

Merging NWELL

Hi,
Can we merge a nwell containing a Thick Oxide gate transistor and other nwell with normal transistor but both the nwell's are at same potenetail? I am getting a DRC error for this case.

Regards,
Dinesh

 

[erikl]

Merging NWELL

Just a guess: The TOX pmos is probably part of the ESD protection structure. During an ESD action, its parasitic pnp junction transistor could create a high density of minority carriers in the nwell, which might affect the normal pmos behavior.
Does the DR violation create a spacing error? May be there's a minimum distance rule for that.

 

[sandeep_torgal]

Re: Merging NWELL

Just a guess: The TOX pmos is probably part of the ESD protection structure. During an ESD action, its parasitic pnp junction transistor could create a high density of minority carriers in the nwell, which might affect the normal pmos behavior.
Does the DR violation create a spacing error? May be there's a minimum distance rule for that.

I guess it has nothing to do with ESD. It might be just a process limitation...

 

[kenliao18]

Merging NWELL

I guess so...

 

[dinesh hegde]

Re: Merging NWELL

Process limitation mean to say any problem in preparing mask, or is there any problem with physics behind this?

Regards,
Dinesh

 

[Colbhaidh]

Re: Merging NWELL

There is no physics reason to not do this. In fact it can be done with no effect, however the thick gate transistor and thin gate transistor would have to be separated by the design rule for the gate oxide mask. A window id drawn where the thin oxide transistors are to be formed. The thick oxide is wet etched off? the mask removed and the thin oxide is grown (which also thickens the thick oxide a wee bit so it is grown a little thinner to compensate). Since this is a wet etch process the width of the window will be larger than drawn so the design rules woud not allow two dissimalilar devices close to one another.
Because the thin transistor and thick transistor receive different threshold adjust and punch through implants it is easier to keep thin and thick devices in different wells but this is really a convenience as typically these wells are at different voltages.

 

[dinesh hegde]

Re: Merging NWELL

Thanks Colbhaidh.

 

[deepak242003]

Merging NWELL

what drc error you are getting.. i suppose you might be getting spacing between the two devies??

 

[kumarans]

Merging NWELL

if u check DRM there will be a rulle for spacing to have different NWell potential

 

[yashiro]

Re: Merging NWELL

I think you should make different NWELL and connect by metal. This should avoid DRC error you get.

 

[prasadneta]

are they digital and analog layouts at same potential?? if so not possible !!or else process error