csjiang
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Dear all:
I have a design with MBIST architecture generated by Mentor Tessent. In the desing my dual port SRAMs are SMIC's 55nm process. The two ports of SRAM can't be read on the same address at the same cycle, unless the clock edge of both ports have been separated certain time. The MBIST pattern have one cycle that read the same address at the same cycle. The clocks edge of both ports in my design are not separated. So the simulation shows Unknown on the read cycle, and the unknown causes simulation error.
I am not expert in Mentor's MBIST tool. Does anyone knows how to escape from MBIST tool generating patterns with the specific condition on testing dual port SRAM?
I have a design with MBIST architecture generated by Mentor Tessent. In the desing my dual port SRAMs are SMIC's 55nm process. The two ports of SRAM can't be read on the same address at the same cycle, unless the clock edge of both ports have been separated certain time. The MBIST pattern have one cycle that read the same address at the same cycle. The clocks edge of both ports in my design are not separated. So the simulation shows Unknown on the read cycle, and the unknown causes simulation error.
I am not expert in Mentor's MBIST tool. Does anyone knows how to escape from MBIST tool generating patterns with the specific condition on testing dual port SRAM?
