There is one problem during LVS process in CALIBRE:
There is one cell in project without real topology (only "abstract" - layout with pins). All the connections checked correctly, except connections to this cell. I.e. unconnected pins couse NO violations.
Is it possible to check connections to black-box cell during LVS in flat or hierarchical mode?
What layout editor are you using? mentor IC station lets you to extract the NETS and connectivity database, with that function you can test the connectivity.