Memory Mapped input/output for modern processor

[rowan.bradley]

I work on a system based on the 8051-family 80C320 processor. It has a 16 address bit 8 data bit bus, plus read/write etc. The IO is all memory mapped. I now want to replace or augment the processor with a new modern processor (an ARM or similar). I still need to use the existing memory mapped peripherals. Ideally I would buy a modern processor board (giving me USB, Ethernet, lots of memory, C compilers, a modern operating system maybe Linux, and if necessary video and sound output, keyboard and mouse input etc.) and interface it to the existing 8051 bus so I can still write to and read from the peripheral registers. Is this possible? What is the best way of designing it? Are some microcontrollers better than others at handling this type of IO? What sort of adapter circuitry would I need to connect the new micro to the old bus? Of course the new processor will be much faster than the old (which runs at 12MHz). I would rather use an off the shelf processor board for the new processor than design it from chips, since that should save a lot of work, and give me a working starting point.

Ideally I would like to be able to read and write to peripheral addresses using a single instruction in the new processor. This (I think) rules out using GPIO pins for the address and data bus, because this would involve a lot of instructions just to do one read or write cycle.

Thanks - Rowan

 

[barry]

Disclosure: I know next to nothing about ARM processors.

But don't they have a bus? APB? If that's too fast, then maybe using GPIO makes sense; you'll just have to write some basic routines to handle data transmission. After all, your peripherals are probably a LOT slower than your new processor and you're going to have to slow stuff down to make it work.

 

[rowan.bradley]

I have found that the TI Stellaris M3 processors seem to have an External Peripheral Interface that sounds as if it does exactly what I want with some nice timing features like a FIFO and non blocking reads. But these parts are marked Not Recommended for New Designs, and none of the newer M4 parts seem to have this EPI. Does anyone know of a current-generation chip that has a feature like this?

Thanks - Rowan