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Large C at input to CMOS gate

danadakk

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Folks seem to like building delays, debounce keys, etc, by placing large C at the
inputs to CMOS gates.

NOT A GOOD IDEA

For case where supply collapse rapid due to its design, load situation.

TI confirms this in an ap note on general CMOS usage. Here is a rough sim of the problem.
Note since spice model did not have the parasitic diodes in it I used external as substitute.
Also used 1 ohm as C ESR......roll your own value(s) for your case. Note using .1 ohms for
CAP ESR produced 3A thru D1......

1710766658741.png



The simple way around this is to place a series R between gate input and the large C.


Regards, Dana.
 
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Too much input C can make added chatter if the input is held in the linear region for longer than ambient noise period and amplitude exceeds any designed hysteresis.
 
Hi,

great discussion.

Some inputs also specify a minimum slew rate. If the input signal is too slow (due to big capacitors), not only the power supply current rises, but also the input may oscillate. Schmitt trigger inputs prevent this.

Klaus
 
I completely agree with the input slew rate discussion. It's not recommended to use input filter capacitors for logic gates unless it has internal (ST gate) or external (latch or monoflop circuit feedback. The problem setup stated in post #1 sounds however rather unrealistic. There are very few situations where you get 50 ns (or < 1 - 10 us at all) supply fall time. I'm not aware of ever having used a circuit which would damage a logic gate with only 100 nF input filter.

A loosely related problem is a reset switch discharging a capacitor. It should have a series resistor to avoid fast degradation of the switch.
 
I'm not aware of ever having used a circuit which would damage a logic gate with only 100 nF input filter.

I haven't experinced any damage which capacitors in the nF ranges as well, and I would consider 100 nF also as rather low. Neverthless, I have used diode "isolated" capacitors in the µF ranges a couple of times at the input of logic gates, to "store" and provide a high level (also without experiencing faults). So far I haven't considered a damage of the logic gate due to a collapse of the supply. So thanks for pointing out.
 
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