Memory Intialization in Xilinx ISE 8.1i Webpack

[sriramsv]

Hi friends,

I've a 16x16 matrix which i need to store in a memory and use the values for my calculation.I'm coding it in Verilog. I'm not sure how to initialize the memory and store it. The Webpack has tools like Core generator and lot other stuffs. Can anyone tell which one to use and how can i initialize the memory!

Thanks
Bye
sriram

 

[echo47]

Several methods available. See the XST User Guide -> HDL Coding Techniques -> RAMs/ROMs -> Initializing RAM.
Version 8.1i partially supports "initial" and "$readmem*", so you can do some initialization in your HDL without using external tools.

 

[sriramsv]

tanx for the info. but the problem is initial and $readmem are not synthesizable codes!

 

[echo47]

Yes they are! Look in the Xilinx manual.

You've probably been reading Verilog textbooks, or listening to Verilog teachers. They perpetuate many mistakes.

 

[ashaheer]

**broken link removed**

 

[echo47]

ashaheer, that V2P manual is ancient history for this discussion.

This works fine in ISE 8.1i, target Spartan-3. Beware that ISE only supports one-dimensional arrays with $readmem (or maybe I just haven't figured out how to get it to work with more dimensions):

module top (clk, out);
  input             clk;
  reg         [7:0] matrix [0:255];
  reg         [3:0] x=0, y=0;
  output reg  [7:0] out;

  initial begin
    $readmemh("mydata", matrix, 0, 255);
  end

  always @ (posedge clk) begin
    {y,x} <= {y,x} + 1;
    out <= matrix[{y,x}];
  end
endmodule

It reads a text file named "mydata" that I filled with 256 random hex values like this:
4C
9F
0C
E7
8E
D8
...

This code doesn't use any special Xilinx tricks, so it also runs fine in ModelSim pre-route and post-route simulation.

By the way, you could replace that $readmemh statement with a bunch of initialization statements like this:
matrix[0] = 'h4C;
matrix[1] = 'h9F;
matrix[2] = 'h0C;
matrix[3] = 'hE7;
matrix[4] = 'h8E;
matrix[5] = 'hD8;
...

 

[hawkbw]

using IP core finish your design

in the step you can initialize your ram with a file
which is *.coe.....

try ...

 

[sriramsv]

tanx guys for yr response, i'll surely try the methods.

 

[aravind]

the initiallization is nothing but rom design.
u can design a rom with all datas r stored.
from there u can access it.
i have one doubt i can access memory my using
reg [7:0] memory [128:0]
command.
but if i wanna read it from there and stored it in ram.
how it possible?
can u give some sample codes.
and also i need copy continiuous using counter.
thanks

 

[echo47]

Yes and no. It is ROM simply because the example code doesn't write to it. But it *could* write to it. Then it would be initialized RAM.

Do you really need to copy the ROM to RAM, or do you simply want to initialize the RAM once before using it?
This example initializes the RAM with some data, and then endlessly increments every RAM byte:

module top (clk, out);
  input             clk;
  reg         [7:0] matrix [0:255];
  reg         [3:0] x=0, y=0, x1=0, y1=0;
  output reg  [7:0] out;

  initial begin
    $readmemh("mydata", matrix, 0, 255);
  end

  always @ (posedge clk) begin
    {y,x} <= {y,x} + 1;             // next address
    out <= matrix[{y,x}];
    x1 <= x;                        // pipeline
    y1 <= y;
    matrix[{y1,x1}] <= out + 1;     // increment the RAM byte
  end
endmodule