process ( not_a_clock_signal ) is
begin
if rising_edge (not_a_clock_signal) then
Q <= D ;
end if ;
end process ;
process ( enable ) is
begin
if enable = '1' then
Q <= D ;
end if ;
end process ;
If you where dealing with an asynchronous FPGA design - which of the above memories would you use?
The clock isn't present at all.
The design is completely asynchronous - in that case would you use latches or FFs ?
The clock isn't present at all.
I would first find a device family that would be appropriate for asynchronous designs, study that architecture and make a decision based on that new understanding. It wouldn't be a simple 'this' or 'that' decision applicable across the board to any type of device.
Kevin Jennings
- Gated clocks are one entry way to learning about the topic called 'hold time violations'.If gated clocks are driven properly, I would say, gated clock design is better for that, than writing data through latch. Gated clocks are not a good practice but it has some benefits though, however it is upto the designer how to gate it.
Pop quiz...explain the basis for your statement...answer the question 'Why?'Final part, gated clocks are better to suit.
I'm sure he did...and I'm sure he appreciated my actual answer as well.Mmm....I think shaiko expects an answer; Perhaps yes or no stuff like FF or gated clock
I disagree with the above statement.The DFF without a clock is not a design and no event triggers
process ( clock ) is
begin
if rising_edge ( some_signal ) then
Q <= D ;
end if ;
end process
That's a strange process indeed: "clock" is in the sensitivity list but you want the data to be sampled with "some_signal"? I can't imagine this working in simulation, let alone being implemented by any hardware at all.In the code below, "some_signal" will trigger the DFF even with the clock at idle.
Code:process ( clock ) is begin if rising_edge ( some_signal ) then Q <= D ; end if ; end process
That's a strange process indeed: "clock" is in the sensitivity list but you want the data to be sampled with "some_signal"? I can't imagine this working in simulation, let alone being implemented by any hardware at all.
You should think in terms of real synthesizable hardware, that's only flip-flops (D, T, JK, SR) and latches - what else?
process ( some_signal ) is
begin
if rising_edge ( some_signal ) then
Q <= D ;
end if ;
end process
Sorry dave9000,
My mistake I meant:
Code:process ( some_signal ) is begin if rising_edge ( some_signal ) then Q <= D ; end if ; end process
- Gated clocks are one entry way to learning about the topic called 'hold time violations'.
- Latches are an entry way to learning about the topic called 'race conditions' or 'logic hazards'
This is not to imply that gated clocks or latches always will lead you down that path, but if you haven't mastered the topics that I mentioned ahead of time, then eventually you will learn about them in a debug situation via your usage of such design elements.
Pop quiz...explain the basis for your statement...answer the question 'Why?'
I'm sure he did...and I'm sure he appreciated my actual answer as well.
Kevin Jennings
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