# Memory in asynchronous FPGA design

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#### shaiko

Code:
process ( not_a_clock_signal ) is
begin
if rising_edge (not_a_clock_signal) then
Q <= D ;
end if ;
end process ;

process ( enable ) is
begin
if enable = '1' then
Q <= D ;
end if ;
end process ;

The first process describes a DFF with a gated clock while the second process describes a transparent D latch.
Am I correct ?

#### K-J

Yes.................

shaiko

### shaiko

Points: 2

#### shaiko

If you where dealing with an asynchronous FPGA design - which of the above memories would you use?

#### xtcx

Gated clock, it is not asynchronous !!!

Anyway,
Both are risky infact, if not used properly. Gated clock\Latch

#### K-J

If you where dealing with an asynchronous FPGA design - which of the above memories would you use?

For starters, I wouldn't deal with an asynchronous FPGA design (at least not with FPGAs as they exist today that I commonly work with...maybe there are some that are good for async designs). But I would use the first memory form that you presented...connected to a free running clock input signal.

Kevin Jennings

#### shaiko

The clock isn't present at all.
The design is completely asynchronous - in that case would you use latches or FFs ?

#### K-J

The clock isn't present at all.
The design is completely asynchronous - in that case would you use latches or FFs ?

I would first find a device family that would be appropriate for asynchronous designs, study that architecture and make a decision based on that new understanding. It wouldn't be a simple 'this' or 'that' decision applicable across the board to any type of device.

Kevin Jennings

shaiko

### shaiko

Points: 2

#### xtcx

The clock isn't present at all.

What do you mean clock is not present. The DFF without a clock is not a design and no event triggers.

If gated clocks are driven properly, I would say, gated clock design is better for that, than writing data through latch. Gated clocks are not a good practice but it has some benefits though, however it is upto the designer how to gate it.

Final part, gated clocks are better to suit.

---------- Post added at 15:42 ---------- Previous post was at 15:40 ----------

I would first find a device family that would be appropriate for asynchronous designs, study that architecture and make a decision based on that new understanding. It wouldn't be a simple 'this' or 'that' decision applicable across the board to any type of device.

Kevin Jennings

Mmm....I think shaiko expects an answer; Perhaps yes or no stuff
like FF or gated clock

#### K-J

If gated clocks are driven properly, I would say, gated clock design is better for that, than writing data through latch. Gated clocks are not a good practice but it has some benefits though, however it is upto the designer how to gate it.
- Gated clocks are one entry way to learning about the topic called 'hold time violations'.
- Latches are an entry way to learning about the topic called 'race conditions' or 'logic hazards'

This is not to imply that gated clocks or latches always will lead you down that path, but if you haven't mastered the topics that I mentioned ahead of time, then eventually you will learn about them in a debug situation via your usage of such design elements.

Final part, gated clocks are better to suit.

Mmm....I think shaiko expects an answer; Perhaps yes or no stuff like FF or gated clock
I'm sure he did...and I'm sure he appreciated my actual answer as well.

Kevin Jennings

shaiko

### shaiko

Points: 2

#### shaiko

The DFF without a clock is not a design and no event triggers
I disagree with the above statement.
In the code below, "some_signal" will trigger the DFF even with the clock at idle.
Code:
process ( clock ) is
begin
if rising_edge ( some_signal ) then
Q <= D ;
end if ;
end process

#### dave9000

##### Full Member level 2
In the code below, "some_signal" will trigger the DFF even with the clock at idle.
Code:
process ( clock ) is
begin
if rising_edge ( some_signal ) then
Q <= D ;
end if ;
end process
That's a strange process indeed: "clock" is in the sensitivity list but you want the data to be sampled with "some_signal"? I can't imagine this working in simulation, let alone being implemented by any hardware at all.
You should think in terms of real synthesizable hardware, that's only flip-flops (D, T, JK, SR) and latches - what else?

#### FvM

##### Super Moderator
Staff member
The signal connected to the clock input of a DFF is analysed as clock by the synthesis tool, in so far you can say, that a DFF doesn't work without a clock.

But your intention is rather clear. I expect, that in an asynchronous design DFFs using "data as clock" would be preferred over latches in most cases. In my opinion, the term "gated clock" doesn't describe the situation well.

I think, the problem could be better dicussed referring to a real asynchronous design example.

shaiko

### shaiko

Points: 2

#### shaiko

That's a strange process indeed: "clock" is in the sensitivity list but you want the data to be sampled with "some_signal"? I can't imagine this working in simulation, let alone being implemented by any hardware at all.
You should think in terms of real synthesizable hardware, that's only flip-flops (D, T, JK, SR) and latches - what else?

Sorry dave9000,
My mistake I meant:

Code:
process ( some_signal ) is
begin
if rising_edge ( some_signal ) then
Q <= D ;
end if ;
end process

#### xtcx

Sorry dave9000,
My mistake I meant:

Code:
process ( some_signal ) is
begin
if rising_edge ( some_signal ) then
Q <= D ;
end if ;
end process

When you put with naming clock, it is by the way we would take it as CLOCK only...
Even if you mention it as some other net, the tool will still take it as clock only, and will calculate timings for this "some_signal" path

But this is not a gated-clock. The figure below is the gated-clock example.
A gated clock terminology is to control the clock flow into one particular network which has only 1 reason to go with "Power Control".

Here your code does latching only ("D" is latched to Q based on some_signal rising event)

I don't see any difference other than the way of coding between your 2 cases, if this some_signal is "Data signal" instead of "clock"

#### Attachments

• gated_clock.jpg
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#### xtcx

- Gated clocks are one entry way to learning about the topic called 'hold time violations'.
- Latches are an entry way to learning about the topic called 'race conditions' or 'logic hazards'

This is not to imply that gated clocks or latches always will lead you down that path, but if you haven't mastered the topics that I mentioned ahead of time, then eventually you will learn about them in a debug situation via your usage of such design elements.

I'm sure he did...and I'm sure he appreciated my actual answer as well.

Kevin Jennings

Yeah yeah...sure he did indeed, but I just meant to say sometimes an answer (yes\no) wouldbe perfect. Also, I brought up the answer with not_clock_signal as a clock but shaiko later confirmed it as a signal.

Cheers...

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