Good FPGA synthesizers support the HDL * multiply operator, and they let you define a RAM in HDL as an array of registers. You may need to write your HDL in a specific way, so refer to your user manual for advice. For example, if you are using Xilinx ISE, then refer to your XST User Guide chapter "HDL Coding Techniques".
I agree with echo, like to add same goes for RAM. If u've written ur HDL as per coding guidelines synth. tool would easily infer embedded RAM block of FPGA. Rather, synth tools are quite mature now so they infer RAM/Multipliers quite easily unless u've written HDL in way which tool vendor have asked NOT to do.. also u can easily instantiate these elements from synthesis library (If using Xilinx/XST, refer lib.pdf for instantiation templet)
thanks guys, so it's either directly by the right "synthesizable" HDL code
or by instantiating on-chip memory (directly or by Core Generator)
or by the off-chip memory (which is a whole different story of course)
Yes, thats correct. And as rightly mmoctar above if you are using Xilinx ISE you can use Language temples (I think under Edit menu) there u'll get what is the right code for infering BRAM & Multiplier for various Xilinx devices. (Though ISE doesn't need any special treatment for multiplication, * operator does infer a multiplier, if available.)