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Measuring the leakage current of an inverter using Cadence Virtuoso

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I have an inverter at a transistor level in Cadence Virtuoso, and I want to measure its leakage current using Spectre simulator. I did a tran analysis and had a source deliver a voltage that will stabilize after some time. The problem is I don't know where to measure the leakage current. Using the to be Plotted option, I can click on the terminals of the Source, Drain and Gate of each the NMOS and PMOS transistors. Is the subthreshold leakage simply the sum of both the Drain currents?
 

Solution
with inverter input=1, pmos drain current gives you the leakage current.
with inverter input=0, nmos drain current gives you the leakage current.

Seperate both mos inputs. Give pmos 1, nmos 0. Then measure nmos or pmos drain current. This is total leakage current.
OK, then I'll try transient analysis. Thank you very much for your answer
 

For single mos IV curves, dc measure is fine. But in your inverter case, check transient currents.
Can you give me an example about the current of the inverter, I'm not very clear how to write code, I'm still a novice how to use HSPICE is not very clear, thank you very much

--- Updated ---


the recommendations I have seen to measure static current in std. cell libraries are usually like this: make a short transient simulation, skip the initial part of the simulation since there is a lot of noise and settling, then average the current value over time for a small time period.
This is my measurement of the current of PMOS about X1. How should I mean it?
 
Last edited:

I would make a single schematic with three items in it.
An inverter with input=vss, an inverter with input=vdd,
and an inverter that is switched though a RZ cycle.

The .op for the first two will give you the static leakages
while the last will give you dynamic power per cycle,
which you can apply to any Hz you like (up to the point
where output fails to settle fully, within the cycle.

I/Os exposed to a more variable input, might want stuff
like biased-at-VOLmax, biased-at-VOHmin added to
the mix.
 

I would make a single schematic with three items in it.
An inverter with input=vss, an inverter with input=vdd,
and an inverter that is switched though a RZ cycle.

The .op for the first two will give you the static leakages
while the last will give you dynamic power per cycle,
which you can apply to any Hz you like (up to the point
where output fails to settle fully, within the cycle.

I/Os exposed to a more variable input, might want stuff
like biased-at-VOLmax, biased-at-VOHmin added to
the mix.
First of all, thank you very much for your answer, but I don't understand it very well. I did a transient analysis of the 4-fan inverter in HSPICE. This is my code. If I want to calculate the average current, I have to determine the value of tcyc. The part of 'from = to =' in meas, but I don't know how to be sure because it affects the magnitude of the current value.

Code:
* VSCNFET Demo: fan-out-4 inverter chain transient simulation

.options POST=2

.param   TEMP=25
.hdl 'vscnfet_1_0_1.va'

.param supply=0.71
.param fo=4
.param tcyc=500p
.param trf=1p

.param supply=0.71
.param Lg=11.7e-9
.param Lc=12.9e-9
.param Lext=3.2e-9
.param s=5e-8
.param Hg=20e-9
.param W=100e-8
.param Geomod=1
.param SDTmod=1
.param BTBTmod=1
.param Rcmod=1
.param Rs0=0
.param Vfbn=0.015
.param Vfbp=-0.015
.param Dia=1.2e-9

.subckt inv vdd in out
xn out in gnd vscnfet_1_0_1 FETtype=1
+Lg=Lg Lc=Lc Lext=Lext s=s Hg=Hg W=W Geomod=Geomod Vfb=Vfbn d=Dia
+SDTmod=SDTmod BTBTmod=BTBTmod Rcmod=Rcmod Rs0=Rs0
xp out in vdd vscnfet_1_0_1 FETtype=-1
+Lg=Lg Lc=Lc Lext=Lext s=s Hg=Hg W=W Geomod=Geomod Vfb=Vfbp d=Dia
+SDTmod=SDTmod BTBTmod=BTBTmod Rcmod=Rcmod Rs0=Rs0
.ends inv

x1 vdd ck in inv m=1
x2 vdd in out inv m='fo'
x3 vdd out n1 inv m='fo*fo'
x4 vdd n1 n2 inv m='fo*fo*fo'
*R n2  0 10k
//cic out gnd 'cic*fo*fo'

vdd vdd gnd 'supply'
vck ck gnd pulse 0 'supply' 'tcyc/2' trf trf 'tcyc/2-trf' tcyc

.meas tran tfall trig v(in) val='supply/2' rise=1
+                  targ v(out) val='supply/2' fall=1
.meas tran trise trig v(in) val='supply/2' fall=2
+                  targ v(out) val='supply/2' rise=2

.tran 0.1p 'tcyc*3'

.plot tran i1_p=par('i(x1.xp.d)')
.print tran i1_n=par('i(x1.xn.d)')
.meas tran avgi1_P avg i(x1.xp.d) from=500ps to=750ps
.meas tran avgi1_N avg i(x1.xn.d) from=500ps to=750ps

.print tran i2=par('i(x2.xp.d)')

.plot tran  i3_p=par('i(x3.xp.d)')
.print tran i3_n=par('i(x3.xn.d)')
.meas tran avgi3_p avg i(X3.xp.d) from=500ps to=750ps
.meas tran avgi3_n avg i(X3.xn.d) from=500ps to=750ps

.print tran i4=par('i(x4.xp.d)')

.end
 

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