cannibol_90
Member level 5
To measure jitter, the following schematic has been used:
![jitter cs vco.jpg jitter cs vco.jpg](https://www.edaboard.com/data/attachments/56/56932-551ef365483f549550c1d06e12930049.jpg)
The Jitter observed was 12.2 ps approximately for 1GHz of data by a PRBS source. With the above schematic, value of jitter reduces when the data rate is increased. How is this possible? Is the above circuit schematic suitable for measuring jitter? Is there any other alternative way to measure jitter in VCOs in AWR?
The schematic of the circuit used is attached.
![jitter cs vco.jpg jitter cs vco.jpg](https://www.edaboard.com/data/attachments/56/56932-551ef365483f549550c1d06e12930049.jpg)
The Jitter observed was 12.2 ps approximately for 1GHz of data by a PRBS source. With the above schematic, value of jitter reduces when the data rate is increased. How is this possible? Is the above circuit schematic suitable for measuring jitter? Is there any other alternative way to measure jitter in VCOs in AWR?
The schematic of the circuit used is attached.
Attachments
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