Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
Actually it can be described in too many ways .....
1. Check your image size and the CPU card's RAM and Flash size
2. Count the ticks taken by each task and compare with the total number of ticks used in a cycle (including the Idle Task)
3. Using VxSim check out how much time your Idle task is there (generally it comes >=70% of your cycle time ---- Depends on Image size and execution time taken by each task with availability of resources)
If the image size is too huge and CPU loading is too high .... then you can go for the SBC's having Higher RAM , Flash and Cache memory(Paging Concept).
Download the source code of uCOS-II, and check the source code of the function OS_TASK_STAT.
It calculates the CPU load in an embedded platform and takes care of integer division and load calculation overflow.
--
Amr Ali www.embedded-tips.blogspot.com
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
