1. A scheme to correlate on both the SOF and PLSCODE differentially is used for frame1 synchronization. The shift registers in the circuit can be partitioned into two sections. The first is associated with SOF, the second with PLSCODE. There are in total 57 taps associated with the 89 registers. In the first part, 25 of them are associated with the pair-wise difference of SOF. In the second part, 32 nonzero taps are associated with PLSCODE since only 32 out of the 64 differentials are known. The taps associated with the shift register for computing the correlation can be obtained as follows. First set all the registers to zero, then shift the modulated SOF and a modulated and scrambled codeword of PLSCODE into the circuit. Once the rightmost register becomes nonzero, the tap associated with a register is just the complex conjugate of the content of the corresponding register. Given that the modulated SOF and PLSCODE take only ±1, ±i, the taps only take these four possible values as well.
2. When used for frame synchronization, the incoming signal arriving at the correlator is2. sampled at one sample per symbol. It is first differentially decoded and the resulting samples are then sequentially shifted into a shift register of length 89. The contents of the shift register are multiplied with the taps. The first 25 and the last 32 values at the output of the multipliers are separately summed together in two different branches. The outputs of the two summers are respectively added and subtracted to produce two values. The maximum of the absolute value out of the two branches is the final output of this correlation circuit.
3. The output is then further processed by a peak search algorithm