As name says "Post Synthesis simulation" is the simulation after synthesis....It is required... because after synthesis our design may not be same as what we thought or what we have design in code...This is because...in synthesis VHDL or verilog code is converted to netlist..This netlist is specific to FPGA device you are using...This unrouted netlist maps our logic to the logic devices available inside FPGA...for example.. if in design you have included NAND gate...it will be mapped to XOR gate where this XOR gate is configured as NAND gate...Basically to validate this new generated un-routed netlist post synthesis simulation is important...