meaning of post synthesis simulation

[alokkmr18]

what exactly meaning of post synthesis simulation ...

right now ..my mentor told me do post synthesis simulation.. i dont why .. i have done my vhdl coding with their functional in modelsim software ..which is properly working ....after that i have done synthesis process in Design complier (synopsys) generated gate netlist in vhdl and verilog both ...
i m using NCSIM tool (ncvhdl) for post synthesis simulation...but i got a one error during my ncelab

ncelab: *E,DLOALB: Design library 'ieee' not defined while reading package ieee.std_logic_1164 (AST).

 

[amitjagtap]

As name says "Post Synthesis simulation" is the simulation after synthesis....It is required... because after synthesis our design may not be same as what we thought or what we have design in code...This is because...in synthesis VHDL or verilog code is converted to netlist..This netlist is specific to FPGA device you are using...This unrouted netlist maps our logic to the logic devices available inside FPGA...for example.. if in design you have included NAND gate...it will be mapped to XOR gate where this XOR gate is configured as NAND gate...Basically to validate this new generated un-routed netlist post synthesis simulation is important...

 

[onion2014]

hi, i am new to asic design flow. I have the following questions. thanks in advance.
1) is post synthesis simulation equal to gate level simulation?
2) post synthesis simulation here means using the gate list and the testbench to perform dynamic simulation?
3) there is formality verification to verify the rtl code and gate list have the same function, right? the formality verification should comes before the DFT or after that DFT?
4)and there are also STA after synthesis, so can we just perform formality verification and STA (i mean either performing gate level dynamic simulation or performing both formality verification and SAT) to verify that after synthesis, the synthesized design still has the same function and satisfies the timing constrains?

As name says "Post Synthesis simulation" is the simulation after synthesis....It is required... because after synthesis our design may not be same as what we thought or what we have design in code...This is because...in synthesis VHDL or verilog code is converted to netlist..This netlist is specific to FPGA device you are using...This unrouted netlist maps our logic to the logic devices available inside FPGA...for example.. if in design you have included NAND gate...it will be mapped to XOR gate where this XOR gate is configured as NAND gate...Basically to validate this new generated un-routed netlist post synthesis simulation is important...

 

[rocking_vlsi]

There are two reasons for post synthesis simulation

1) Synthesis and simulation mismatch : Your synthesized netlist might not behave functionally as expected.
2) Timing simulation : https://digitalelectronics.blogspot.in/2006/10/gate-level-simulation-introduction.html

 

[rca]

Doing post layout simulations are useful for power estimation.
Normally the functionality equivalency will be covered by a LEC tool.
The dft insertion will be checked by the fact you are able to generate the patterns and able to simulate them.
Simulate the patterns and functional tests with min max delay, improve your confidence.