I don't see a big practical difference and won't think about the principle nature when designing FSMs. In so far, I agree with treqer. In some cases it may be interesting to know, if and how many additional registers are created by the registered outputs and how they behave in case of timing violations.
The Medvedev prototype I've seen in literature has the output signals identical with state variable bits. In a VHDL design, the state variable is preferably an enumeration. You would write separate assignments for the registered output signals and leave it to the synthesis tool to merge them with the state variable bits if possible. In other words, you don't exactly know, if additional registers are generated when only looking at the code. In the "registered ouput " Mealy case, the right hand side of output assignments is different from state variable assignments, so additional registers are created anyway.