May calibre run LVS check in mixed-signal design?

Status
Not open for further replies.
H

harryzhu

Member level 3
Joined
Oct 9, 2004
Messages
59
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,286
Activity points
627
In mixed-signal design, there's schematic in analog part, and verilog netlist in digital part, may calibre run LVS check based on this condition? How can I do it? Thanks for your help!
 

Calibre has a tool to change verilog to spice. But you need the spice netlist for each standard cell definition.
 

I run v2lvs to convert verilog to cdl netlist by using as this:

v2lvs -lsp stdcell.v -lsp *v -o output.cdl -s0 gnd -s1 vdd -v top_verilog.v

But I met another question, since I define the bus such as cir[0-31], and which is not recognized, how can I resolve it?

I know there's another way to run LVS using dracula in mixed-signal design, but I don't know the detailed flow.
 

Status
Not open for further replies.

Similar threads

Menu
Log in
Register
Cookies are required to use this site. You must accept them to continue using the site. Learn more…