maximum width of transistor in 90nm process

[gavanbash]

Hi
I designed an opamp which has four transistor that their width are 300 um.My quastion is that when I'm using 90nm CMOS process in my project, having transistors with this width(during drawing layout and fabrication) make problem or not?
Does this amount for width is huge or not?

 

[ThisIsNotSam]

run a DRC check or read the documentation. We can't know what technology you are talking about given the information you have shared.

 

[gavanbash]

I'm at design level and I want to know if this size is large I test another design procedure.

 

[ThisIsNotSam]

I'm at design level and I want to know if this size is large I test another design procedure.

as I said, check the documentation. the answer is there.
you can always use IO-like transistors if you need really big devices.

 

[dick_freebird]

It may or may not be "large" depending on how it
was laid out; multifinger would be much, much
better than single stripe. It could be legal in any
case if "taps" were close-in, and if the foundry did
not assert W-limit rules to complement the limits
of model extraction geometries.

Issues about very wide single stripe devices include
debiasing and electromigration, and gate resistance.
Even if Rg is modeled (lump style) the distributed
nature of it will impact high frequency operation.
Maybe a "don't-care" for an op amp.

But I'd recommend making it multifinger in any case.