jucampos
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Hi,
I'm designing a oscillator for an ultra low power/voltage application, and I have some problems to define the maximum phase noise that is necessary to avoid the ADC(sigma-delta) resolution degradation. The intention is to design a 16KHz oscillator, that will be used with a 14 bits ADC, with 1KHz bandwidth and 16KHz of oversample. Will be used a Continuous time modulator that is more sensible to the jitter interference.
Thus, i would like to know the maximum limit for the phase noise. During my studies, I verified that this parameter needs to be comparable to quantization noise, but I don't understand what this mean exactly. Since the phase noise is given in dBc/Hz, what is the relation that can be done with the quantization noise? In which frequency should I compare those values to verify the precision of my oscillator.
Thanks in advance.
Juliana
I'm designing a oscillator for an ultra low power/voltage application, and I have some problems to define the maximum phase noise that is necessary to avoid the ADC(sigma-delta) resolution degradation. The intention is to design a 16KHz oscillator, that will be used with a 14 bits ADC, with 1KHz bandwidth and 16KHz of oversample. Will be used a Continuous time modulator that is more sensible to the jitter interference.
Thus, i would like to know the maximum limit for the phase noise. During my studies, I verified that this parameter needs to be comparable to quantization noise, but I don't understand what this mean exactly. Since the phase noise is given in dBc/Hz, what is the relation that can be done with the quantization noise? In which frequency should I compare those values to verify the precision of my oscillator.
Thanks in advance.
Juliana
