Maximum frequency on the board

[HyperText]

Hi,

I realised the pipeline that I talked before (https://www.edaboard.com/threads/275809/), but now I have some doubts on the maximum frequency.
I have a Spartan-3E FPGA running at 50MHz and I want to test my pipeline on it. I linked the output result with the 7-segments display and all works "fine" (I'll explain this a bit after).

The problem is: how can I calculate the maximum frequency?
I added a DCM in my design, because I already know that my pipeline has to work below the 50MHz frequency.
Let's say I tried with 20MHz (base_clock / 2.5): I tested my project on the FPGA, but sometimes the result is wrong.
Fine... I put a 20ns (50MHz) constraint for the base clock (that I repeat works at 50MHz and it's called "clk_in") and in the Post-PAR (Place and Route) I find this:

Derived Constraint Report
Derived Constraints for TS_clk_in
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
| | Period | Actual Period | Timing Errors | Paths Analyzed |
| Constraint | Requirement |-------------+-------------|-------------+-------------|-------------+-------------|
| | | Direct | Derivative | Direct | Derivative | Direct | Derivative |
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
|TS_clk_in | 20.000ns| 6.000ns| 21.765ns| 0| 20| 0|163484298872214|
| TS_Clock_DCM_CLKDV_BUF | 50.000ns| 54.413ns| N/A| 20| 0|163484298872214| 0|
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+

1 constraint not met.


Data Sheet report:
-----------------
All values displayed in nanoseconds (ns)

Clock to Setup on destination clock clk_in
---------------+---------+---------+---------+---------+
| Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
clk_in | 54.413| | | |
---------------+---------+---------+---------+---------+


Timing summary:
---------------

Timing errors: 20 Score: 41134 (Setup/Max: 41134, Hold: 0)

Constraints cover 163484298872214 paths, 0 nets, and 6552 connections

Design statistics:
Minimum period: 54.413ns{1} (Maximum frequency: 18.378MHz)


------------------------------------Footnotes-----------------------------------
1) The minimum period statistic assumes all single cycle delays.

So it seems fine to me that if I "run" my project a 20MHz, and not 18.378MHz, it doesn't work properly.
Ok, so I tried with 15MHz and it still doesn't work (sometimes the pipeline output is wrong).
Then I tried with 12.5MHz and it's the same.
My pipeline works only at 10MHz (and below)... Why? How can I justify the discrepancy of about 8MHz from the report and the "practice"? And how can I "predict" it instead of going with multiple attempts (lowering the frequency)?

Thanks

 

[barry]

What do you mean "my pipeline only works at 10 MHz"? What do you mean "test my pipeline"?


Right there in your timing summary it says "Maximum frequency: 18.378MHz". that means it WON'T WORK above that frequency. Did you assign appropriate timing constraints to your design? If it doesn't meet those constraints then you need to go back and figure out WHY it doesn't and make the necessary changes.

 

[HyperText]

"my pipeline only works at 10 MHz" means that if I set the clock to 10MHz, it never fails to produce the result.
"test my pipeline" means that I see the pipeline output on the 7-segments display.

I don't know HOW I can figure out what I have to change :\
Any hint?

By the way, if useful, this is the Post-PAR report: https://pastebin.com/raw.php?i=qQ8QNhvs

 

[mrflibble]

Uhm...

Data Path Delay: 54.335ns (Levels of Logic = 46)

Ouch!

I see lots of paths with 45 and 46 levels of logic in that post-par report. That explains why you get such large data path delays. And as such low operating frequency. I suspect your pipeline may need some more pipelining, possibly between stage 1 and 2.

 

[HyperText]

Yeah, I know it's very slow because I used a MAC multiplier (signed 16 bit) I can't use any other multipliers (especially the ones embedded in the FPGA that are VERY FAST), so I have to arrange like that

The data path delay is 54.335ns <=> ~18MHz, but it's a "lie", because I need to run my pipeline at 10MHz
I don't know how I can figure out the problem...

 

[barry]

Forgetting for the moment that 46 logic levels is pretty enormous, if your timing report says that your maximum frequency is 18Mhz, then you SHOULD be able to run at 18MHz. You either don't have this constrained properly or perhaps you've got some synchronization (clock-boundary crossing) problem?

 

[joelby]

Just because the longest path says it will run at 18MHz doesn't mean the whole design will. If you wanted it to run at 18 I would adjust the constraint (and DCM?) and try to place and route the design again. Generally, all bets about maximum frequency are off if the design fails to meet timing.