Maximum Clock frequency of Seq circuit

[asicganesh]

maximum frequency of a circuit

1) Are their any ways to increase the maximum clock frequency of a sequential circuit?
Is it only by introducing clock skew

2) What should one do if post-synthesis the maximum frequency expected is not met?
Should we find slowest paths and try to optimise them.. in that case what all optimisation?

 

[useless_skew]

how to find maximum clock frequency

1) To increase the maximum clock frequency,
we can decrease the data path delay or increase the clock skew,
improve placement and routing so that the net delay is less,
use low-vt cells for the critical path.
move to other technology if you are free to change the technology. (Ex: 90nm to 45 nm),

2) Check whether the violation is real.
Identify the weak cells and try to do optimizations like buffer insertion, cell sizing, logic optimization, pin swapping, cloning.