Maximum charge that can be stored in the capacitor if the word line...

[Oceanamie]

What is the maximum charge that can be stored in the capacitor if the word line for write is set at 2 V?

This is for 1T1C DRAM. I have the values, but I want to solve it on my own but don't know how to. Need help, please.

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I have solved this, now I need to know.

I have a 1T1C DRAM, 10 fF capacitor with Vt ~ 1 V.

How often does this this individual cell need to be refreshed in order for the charge stored not to drop below 85% of its maximum value?

 

[dick_freebird]

You need to say what the leakage current is.

 

[Oceanamie]

You need to say what the leakage current is.

This is what I'm trying to solve. Not sure what to do. I know the charge at points and temperature, but can't find the rest. Need to know the equation or method, and I'm sure I can solve it.

 

[dick_freebird]

Refresh time is set -by- the (worst case) leakage current.
You can't solve one equation with two unknowns.

A "typical" device is not what you should predicate this
design question on. You need to know the yield-limiting
devices' contribution (switch, cap self-leakage, etc.)
which means you're looking for the n-sigma leakage tails
@ temp @ supply @ processing corner (n following bit
count - how many sigma is 1/1Gb telling you?

 

[erikl]

... can't find the rest. Need to know the equation or method ... View attachment 95362

Just a calculation example:

Say your worst case leakage current Il = -5e-10A (398 K curve @ V_GS=-1V),
then the C discharge rate is δV/δt = Il/C = -5e-10A/(10e-15 As/V) = -50mV/µs .

Say the original capacitor voltage is 2V , then discharge to 85% is 1.7V , the difference being 300mV .
To discharge the capacitor of these 300mV by the above discharge rate takes
300mV / |-50mV/µs| = 6µs

Your refreshing time must be shorter, say 5µs => refreshing rate = 200 kHz .