In my design I need to give a clk input signal to 3 diferents Analog to Digital Converters. I'm thinking of using a PLL External Clock Output (signal PLL_L_CLKOUTp of the FPGA) to give the clock to these 3 converters.
There is only 1 output of this type with this FPGA.
I'll like to know if there is any recommendations using this output signal to fed 3 diferents Analog to Digital Converters ? (fanout , layout for exemple)
Is this a good way to do it ?
Maybe driving the PLL output to 3 diferents standard fast I/O pins (1 pin for 1 DAC) is a better design ?
Hi,
The output signal of the FPGA internal PLL will be use to give the clock (100 MHz to 130 MHz) to 3 Analog to Digital Converters (AD9433).
The output level is 0 V / +5 V.
I don't know if there is any particular requirements using this ADC (Didn't see anything in the datasheet).
Thank you for your help.
For AD9433, I would use a high level (e.g. +/- 2.5 V or +/- 3.3V) differential clock output, capacitive coupling to match the common mode range, source side 2x50 series termination, differential 100 ohms party line passing all three ADCs, 100 ohm end termination.
No. Read the datasheet. 5V will hardly fit a FPGA or other high speed data sink.
Only the analog input uses 5V. The clock input is 5V capable, but can be supplied with lower logic level, utilizing the differential input buffer and capacitive coupling if necessary.
Hard job.
High sampling rate, 3 devices in parallel, databus 3 x parallel...expect trouble in PCB layout routing and data processing.
I've done a project with similar requirement. I've chosen LTC2172. One device, 4 channel simultaneous sampling with LVDS interface.
I think this is more simple and the more reliable, too. Take a look at it's datasheet, maybe it fits your needs.
Most convincing point for me would be that LTC2174-12 (4x12-bit 100 MHz) price is less than two AD9433-100. But it's 1.8 versus 5V technology which impacts on the analog design in several regards. The respective 600 MHz LVDS data rate is already at the edge of MAX10 speed, 750 MHz for the 125 MHz ADC version far beyond.
Interfacing AD9433 100/125 MHz fully parallel interface is relative easy in comparison.
Good tip ! I didn't know those circuits actually exists.
To run my tests I'm gonna use a component of this familly (Texas Instruments): "CDCLVC11xx 3.3-V and 2.5-V LVCMOS High-Performance Clock Buffer Family"
I'll keep you posted of the tests and solution I'll be choosing.