Max operating frequency of IP on FPGA

[shitansh]

Hi all,

Can any body tell me, How to calculate or know that, on what max frequency designed IP will work on FPGA? Does max freq is dependent on FPGA switching matrix speed?

For digital design max freq can be calculated from clk-out + propogation delay of output logic, where clock to outof filp-flop (in case of ASIC) is given by manufacturure, what in case of FPGA?

Thanks,
Shitansh Vaghela

 

[philoman]

you can get the datasheet from the manufacturer's website, in which typical performance data may be available

 

[amraldo]

When you synthesize a design to FPGA, synthesizer tells you what max clock it can accpet.
--
Amr Ali

 

[farhada]

IPs on FPGA depends on a lot of different things, the architecture of the FPGA, the way the synthesizer does the synthesis, the technology of the FPGA and how the code is written when it is mapped into the FPGA's architecture.
You can trust the results of the syntheses program (if you have access to the code) or the if you instantiate the IP on a FPGA then you can use the report from the FPGA tool to give you a more accurate values.

 

[shitansh]

You can trust the results of the syntheses program (if you have access to the code) or the if you instantiate the IP on a FPGA then you can use the report from the FPGA tool to give you a more accurate values.

Hi Farhada,

Syntheses report is varies according to gevien constraint for IO interface. If i change input delay and output delay in SDC file then in report FMAX varies. This i am not understanding why?

My target is how to apply proper constraing to IP so that it can be port to any FPGA say Xilinx or ACTEL or Altera.

I do agree that perfomance will vary on different FPGA technology, and some typical coding style we have to forllow which are technology dependent, i am taking care of that.

Can you suggest me something for that.

Thanks,
Shitansh Vaghela