Hello shan14,
in regards to your code, did you synthesize it successfully? I just copy and paste the code and I got an error due to size mismatch. It is just the size of "t1", you have to set it to 2 downto 0.
From my point of view, there are couple of things I would coded differently. In the process sensitivity list, I would put just the clock signal and reset. I think, maybe you can put the assignation "output_there <= '1'" inside the "elsif(rising_edge(clk)) then".
Also, as TrickyDicky suggested you, a testbench is the best way to test if your design behaves as you expect
Best regards.