Matrix Multiplication in Vhdl

[Eddy786]

Hi Folks,

I would like to perform matrix multiplication in Vhdl,I have to save the end product in RAM.

Thanks in advance.

 

[TrickyDicky]

Let us know how you get on.

 

[Eddy786]

My input matrix is of 4*6 and coefficient matrix is of 6*4.Resultant matrix should be of 4*4,the coefficient matrix is in ROM, can we do this without for loop.

 

[FvM]

As you want ROM coefficients and result in RAM, the calculation has to be performed sequentially, one term per clock cycle.

 

[TrickyDicky]

My input matrix is of 4*6 and coefficient matrix is of 6*4.Resultant matrix should be of 4*4,the coefficient matrix is in ROM, can we do this without for loop.

Using a loop is a behavioural way of doing it, or a way to make a massively parallel circuit. If you did use a loop, you would quickly run out of resources as the matrices got bigger.

As FvM said, you need to do it sequentially. I highly suggest you step back from the code, and draw a circuit diagram of your intended design.

 

[Eddy786]

I am able to design the flow diagram of my intended problem, now i want to read my coefficient matrix in ROM, for this matrix i have created a matlab script and put the data into a text file, does anyone knows how i can read this file into ROM and also i need to put 2 coefficient in one memory location.

 

[FvM]

Unlike Verilog $readmemb(), there's no standard method to import ROM data to design tools. Some tools understand VHDL files for inferred ROM, some can import hex files for vendor ROM macros. Generating a *.VHD file with a constant array is probably the most portable method.

 

[Eddy786]

This means you are trying to say that i need to put the hardcode values directly in ROM in vhdl script, not loading data from file.

 

[TrickyDicky]

What are you portability requirements? If you're using a single board, you can probably just use the vendor's prefered method of loading a rom.

 

[Eddy786]

I am using controller to calculate rom address and sending it to rom but due to memory timing issue I am not able to get the correct value out of memory, my memory output is going to mux to select upper and lower bit, how can I latch a correct value without violating setup and hold time.

 

[TrickyDicky]

Why not put some pipelining in it?

 

[Eddy786]

Did you mean i have to put a register between rom and mux or rom and controller.please elaborate.

 

[ads-ee]

Did you mean i have to put a register between rom and mux or rom and controller.please elaborate.

Yes he means exactly that. That is what pipelining means to add registers to break up a long combinational path between registers into smaller ones so they can meet setup/hold timing.

 

[Eddy786]

Yes he means exactly that. That is what pipelining means to add registers to break up a long combinational path between registers into smaller ones so they can meet setup/hold timing.

Hi ,

I am able to solve this but not with pipelining but calculating the address on the falling edge and reading the data on positive edge.With this i am to remove setup and hold constraint.Thanks anyway.

 

[TrickyDicky]

Using the double edge setup, you need even more constraints, and you actually impose stricter constraints on the design!