Matrix in Xilinx 2v6000- need advice on VHDL code

Matrix in Xilinx 2v6000

hello,
I'm trying to write a VHDL code able to have in input a logic vector of 4 bits and store them in a matrix. The problem is that I've to store 8 bit (that represent a pixel information in gray scale). So i've to wait 2 clocks in order to have my 8 bits to save in a matrix with 100 rows (that represent # of frames) and 8 columns (that represent my 8 bit of pixels information). I hope to have explain my problem clear. I'm working to my first vhdl code. Can you give me some tips? thanks a lot

draft:
architecture Behavioral of acquaria is
signal FRAMECNT : std_logic_vector (6 downto 0):= "0000000";
signal PIXIN : std_logic_vector (3 downto 0):= "0000";
signal PIXINCNT : std_logic_vector (8 downto 0):= "000000000";
process (QCLK)
begin
--reset of pixin when I've received 100 frame
if (FRAMECNT ="1100100") then -- Matrix reset

--PIXEL reading: 4 BIT NIBBLE MSB FIRST
if (QCLK = '1' and QCLK'event) THEN
PIXIN(3 down to 0) <= PIXIN4;
wait until rising_edge(QCLK)
PIXIN(7 downto 4) <= PIXIN4;
--here I've to put pixin in a matrix row
end if;
--reset of pixin when I've received 8 bit
if (PIXINCNT ="1000") then PIXIN <= reset; end if;
end process;