matrices input for vhdl code

[Farid Ishak]

hi..
i have problem
1. on how to design input for matrices to insert to my coding (1D) then
2. code for transpose module of the matrices

sory i have problem in attach the file ..so i copy my code below :

LIBRARY ieee;
USE ieee.std_logic_1164.all;

LIBRARY work;

ENTITY haar IS
PORT
(
clk : IN STD_LOGIC;
in0 : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
in1 : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
in2 : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
in3 : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
in4 : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
in5 : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
in6 : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
in7 : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
out0 : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
out1 : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
out2 : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
out3 : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
out4 : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
out5 : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
out6 : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
out7 : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END haar;

ARCHITECTURE bdf_type OF haar IS

COMPONENT daftar
PORT(clk : IN STD_LOGIC;
i : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
o : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT;

COMPONENT purata
PORT(clk : IN STD_LOGIC;
a : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
b : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
c : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT;

COMPONENT beza
PORT(clk : IN STD_LOGIC;
a : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
b : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
c : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT;

SIGNAL SYNTHESIZED_WIRE_36 : STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL SYNTHESIZED_WIRE_37 : STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL SYNTHESIZED_WIRE_38 : STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL SYNTHESIZED_WIRE_39 : STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL SYNTHESIZED_WIRE_40 : STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL SYNTHESIZED_WIRE_41 : STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL SYNTHESIZED_WIRE_42 : STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL SYNTHESIZED_WIRE_43 : STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL SYNTHESIZED_WIRE_44 : STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL SYNTHESIZED_WIRE_45 : STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL SYNTHESIZED_WIRE_46 : STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL SYNTHESIZED_WIRE_47 : STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL SYNTHESIZED_WIRE_48 : STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL SYNTHESIZED_WIRE_49 : STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL SYNTHESIZED_WIRE_26 : STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL SYNTHESIZED_WIRE_27 : STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL SYNTHESIZED_WIRE_28 : STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL SYNTHESIZED_WIRE_29 : STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL SYNTHESIZED_WIRE_30 : STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL SYNTHESIZED_WIRE_31 : STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL SYNTHESIZED_WIRE_32 : STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL SYNTHESIZED_WIRE_33 : STD_LOGIC_VECTOR(7 DOWNTO 0);


BEGIN



b2v_inst : daftar
PORT MAP(clk => clk,
i => in0,
o => SYNTHESIZED_WIRE_36);


b2v_inst1 : purata
PORT MAP(clk => clk,
a => SYNTHESIZED_WIRE_36,
b => SYNTHESIZED_WIRE_37,
c => SYNTHESIZED_WIRE_42);


b2v_inst10 : purata
PORT MAP(clk => clk,
a => SYNTHESIZED_WIRE_38,
b => SYNTHESIZED_WIRE_39,
c => SYNTHESIZED_WIRE_46);


b2v_inst11 : purata
PORT MAP(clk => clk,
a => SYNTHESIZED_WIRE_40,
b => SYNTHESIZED_WIRE_41,
c => SYNTHESIZED_WIRE_47);


b2v_inst12 : purata
PORT MAP(clk => clk,
a => SYNTHESIZED_WIRE_42,
b => SYNTHESIZED_WIRE_43,
c => SYNTHESIZED_WIRE_48);


b2v_inst13 : beza
PORT MAP(clk => clk,
a => SYNTHESIZED_WIRE_36,
b => SYNTHESIZED_WIRE_37,
c => SYNTHESIZED_WIRE_30);


b2v_inst14 : beza
PORT MAP(clk => clk,
a => SYNTHESIZED_WIRE_44,
b => SYNTHESIZED_WIRE_45,
c => SYNTHESIZED_WIRE_31);


b2v_inst15 : beza
PORT MAP(clk => clk,
a => SYNTHESIZED_WIRE_38,
b => SYNTHESIZED_WIRE_39,
c => SYNTHESIZED_WIRE_32);


b2v_inst16 : beza
PORT MAP(clk => clk,
a => SYNTHESIZED_WIRE_40,
b => SYNTHESIZED_WIRE_41,
c => SYNTHESIZED_WIRE_33);


b2v_inst17 : purata
PORT MAP(clk => clk,
a => SYNTHESIZED_WIRE_46,
b => SYNTHESIZED_WIRE_47,
c => SYNTHESIZED_WIRE_49);


b2v_inst18 : purata
PORT MAP(clk => clk,
a => SYNTHESIZED_WIRE_48,
b => SYNTHESIZED_WIRE_49,
c => SYNTHESIZED_WIRE_26);


b2v_inst19 : beza
PORT MAP(clk => clk,
a => SYNTHESIZED_WIRE_42,
b => SYNTHESIZED_WIRE_43,
c => SYNTHESIZED_WIRE_28);


b2v_inst2 : daftar
PORT MAP(clk => clk,
i => in1,
o => SYNTHESIZED_WIRE_37);


b2v_inst20 : beza
PORT MAP(clk => clk,
a => SYNTHESIZED_WIRE_46,
b => SYNTHESIZED_WIRE_47,
c => SYNTHESIZED_WIRE_29);


b2v_inst22 : beza
PORT MAP(clk => clk,
a => SYNTHESIZED_WIRE_48,
b => SYNTHESIZED_WIRE_49,
c => SYNTHESIZED_WIRE_27);


b2v_inst23 : daftar
PORT MAP(clk => clk,
i => SYNTHESIZED_WIRE_26,
o => out0);


b2v_inst24 : daftar
PORT MAP(clk => clk,
i => SYNTHESIZED_WIRE_27,
o => out1);


b2v_inst25 : daftar
PORT MAP(clk => clk,
i => SYNTHESIZED_WIRE_28,
o => out2);


b2v_inst26 : daftar
PORT MAP(clk => clk,
i => SYNTHESIZED_WIRE_29,
o => out3);


b2v_inst27 : daftar
PORT MAP(clk => clk,
i => SYNTHESIZED_WIRE_30,
o => out4);


b2v_inst28 : daftar
PORT MAP(clk => clk,
i => SYNTHESIZED_WIRE_31,
o => out5);


b2v_inst29 : daftar
PORT MAP(clk => clk,
i => SYNTHESIZED_WIRE_32,
o => out6);


b2v_inst3 : daftar
PORT MAP(clk => clk,
i => in2,
o => SYNTHESIZED_WIRE_44);


b2v_inst30 : daftar
PORT MAP(clk => clk,
i => SYNTHESIZED_WIRE_33,
o => out7);


b2v_inst4 : daftar
PORT MAP(clk => clk,
i => in3,
o => SYNTHESIZED_WIRE_45);


b2v_inst5 : daftar
PORT MAP(clk => clk,
i => in4,
o => SYNTHESIZED_WIRE_38);


b2v_inst6 : daftar
PORT MAP(clk => clk,
i => in5,
o => SYNTHESIZED_WIRE_39);


b2v_inst7 : daftar
PORT MAP(clk => clk,
i => in6,
o => SYNTHESIZED_WIRE_40);


b2v_inst8 : daftar
PORT MAP(clk => clk,
i => in7,
o => SYNTHESIZED_WIRE_41);


b2v_inst9 : purata
PORT MAP(clk => clk,
a => SYNTHESIZED_WIRE_44,
b => SYNTHESIZED_WIRE_45,
c => SYNTHESIZED_WIRE_43);


END bdf_type;

 

[barry]

What is your question? You don't tell us anything about your components, errors or problems.

First of all, you can create an ARRAY like this:

type arr_type is array (7 downto 0) of std_logic_vector(7 downto 0);
signal my_array:arr_type;

 

[Farid Ishak]

What is your question? You don't tell us anything about your components, errors or problems.

First of all, you can create an ARRAY like this:

type arr_type is array (7 downto 0) of std_logic_vector(7 downto 0);
signal my_array:arr_type;

thanks for reply,

my question is how to insert matrices row by row into my code.

the code is about haar transform, diff,average

 

[Farid Ishak]

i got this code.. but there is error .. its said to "....many to fit in 385 availbale.." maybe because of the loop problem.. i dont have any idea to fix it.
2nd is how to make output from below code to feed above code?

package newtype is
type row_t is array(0 to 3) of integer;
type matrix_t is array(0 to 3, 0 to 3) of integer;
end newtype;

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.newtype.all;

entity test is
port(input: in integer RANGE -127 to 127;
output: out matrix_t;
clk: in std_logic);
end test;

architecture arch of test is

signal matrix : integer range -127 to 127;
signal temp_row : row_t;
signal count : unsigned(1 downto 0) := "00";

function extract_row( m : matrix_t; row : integer) return row_t is
variable ret : row_t;

begin
for i in row_t'range loop
ret(i) := m(row, i);
end loop;

return ret;
end function;

begin

process(clk)
begin
if rising_edge(clk) then
temp_row <= extract_row( matrix, to_integer(count) );
count <= count + 1;
end if;
end process;
end arch;

 

[barry]

I can't figure out what you are doing here, but it sounds like you're trying to more registers than are available in the device. Maybe you should use memory. What device are you targeting?

On every clock edge, you are going to execute your function extract_row-not sure that's valid. And you are going to do this forever.

Can you explain what you are actually trying to do?

 

[Farid Ishak]

thanks for reply..

the device is cyclone II starter kit altera

what im try to do is the feed up haar with the matrix number row by row..

 

[barry]

Is the matrix constant? If so, then you can just generate a ROM (using Altera's IP tools).