If you have a complex design and you want to test it thoroughly then you can use MATLAB to generate a large set of inputs and corresponding outputs.Most of the functions are inbuilt in MATLAB and the matrices can be solved very easily.So it is very easy to write a code in MATLAB which does the same function in VHDL.
Once the set of inputs is generated copy these into a testbench program and run the simulation.If the outputs obtained matches with that of MATLAB then your VHDL design is correct.This is a manual way of checking.
If you want to do it in a automatic way you can use "assert" statement available in VHDL for knowing the possible errors.Since file handling is easy in MATLAB you can write a code in MATLAB so that it generates a testbench file.It will look something like this:
input <="10100101";
assert output /= MATLAB_output report "error";
Here 'input' is the applied input to the design.
'output' is the output of the design.
MATLAB_output is the output obtained by running the code in MATLAB.This has to be properly replaced by the output matrix values.
--vipin
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