Matlab + ISE simulator

[lorf_of_the_rings]

hello all,,,
I heard that is possible to use matlab to generate a vector file and use this vector file in testbench module for testing an FPGA module,,,
is that achievable and how to do that,,,

thank you in advance

 

[fcfusion]

Yes, it is possibly and I use that all the time. It's very usefull.

MatLab allows you to create and write files using code that is very similar to C programming (fopen(), fprintf(),fclose,etc.).

Verilog also as a syntax simillar to C programming ($fopen(),$fread(),$fclose()).

VHDL has some read and write functions has well but I don't know how to use them because I only code in Verilog.

Peace man

 

[vipinlal]

If you have a complex design and you want to test it thoroughly then you can use MATLAB to generate a large set of inputs and corresponding outputs.Most of the functions are inbuilt in MATLAB and the matrices can be solved very easily.So it is very easy to write a code in MATLAB which does the same function in VHDL.
Once the set of inputs is generated copy these into a testbench program and run the simulation.If the outputs obtained matches with that of MATLAB then your VHDL design is correct.This is a manual way of checking.

If you want to do it in a automatic way you can use "assert" statement available in VHDL for knowing the possible errors.Since file handling is easy in MATLAB you can write a code in MATLAB so that it generates a testbench file.It will look something like this:

input <="10100101";
assert output /= MATLAB_output report "error";

Here 'input' is the applied input to the design.
'output' is the output of the design.
MATLAB_output is the output obtained by running the code in MATLAB.This has to be properly replaced by the output matrix values.

--vipin
https://vhdlguru.blogspot.com/

 

[lorf_of_the_rings]

Yes, it is possibly and I use that all the time. It's very usefull.

MatLab allows you to create and write files using code that is very similar to C programming (fopen(), fprintf(),fclose,etc.).

Verilog also as a syntax simillar to C programming ($fopen(),$fread(),$fclose()).

VHDL has some read and write functions has well but I don't know how to use them because I only code in Verilog.

Peace man

Thank gor ur fast response ,,, and i am sorry i didn't mentioned that i am using Verilog,, not VHDL,,
I generate a wave form of sine wave using Matlab, and i want to use the file i generated in the testbench,, the file is consist of stream of bytes that represent the sine wave.
how can i handel that file in verilog?

Added after 35 minutes:

If you have a complex design and you want to test it thoroughly then you can use MATLAB to generate a large set of inputs and corresponding outputs.Most of the functions are inbuilt in MATLAB and the matrices can be solved very easily.So it is very easy to write a code in MATLAB which does the same function in VHDL.
Once the set of inputs is generated copy these into a testbench program and run the simulation.If the outputs obtained matches with that of MATLAB then your VHDL design is correct.This is a manual way of checking.

If you want to do it in a automatic way you can use "assert" statement available in VHDL for knowing the possible errors.Since file handling is easy in MATLAB you can write a code in MATLAB so that it generates a testbench file.It will look something like this:

input <="10100101";
assert output /= MATLAB_output report "error";

Here 'input' is the applied input to the design.
'output' is the output of the design.
MATLAB_output is the output obtained by running the code in MATLAB.This has to be properly replaced by the output matrix values.

--vipin
https://vhdlguru.blogspot.com/

thank you so much,,
how and where i can copy the set of inputs in the testbench file?
and is there way to do the automatic checking using verilog?

 

[fcfusion]

I generate a wave form of sine wave using Matlab, and i want to use the file i generated in the testbench,, the file is consist of stream of bytes that represent the sine wave.

Well, thats exactly what I do too. I generate a sine wave in Matlab and use it to test my digital sigma-delta.

This is how you should do:

1) create a vector to store your entire wave. For example:

reg [15:0] sine_wave [0:999]; //1000 registers with 16 bit each

2) Read from file and store values in your registers:

integer file_ptr;
integer i;

initial
begin
file_ptr=$fopen("c:\...whatever...\sin.txt","r"); //can open any file type you want

for (i=0;i<1000;i=i+1) begin
$fread(sine_wave,file_ptr);
end;

end;

This should work, but check the syntax, I'm not sure everything is right.

 

[Anuja Diggikar]

Yes, it is possibly and I use that all the time. It's very usefull.

MatLab allows you to create and write files using code that is very similar to C programming (fopen(), fprintf(),fclose,etc.).

Verilog also as a syntax simillar to C programming ($fopen(),$fread(),$fclose()).

VHDL has some read and write functions has well but I don't know how to use them because I only code in Verilog.

Peace man

hello
while searching solution for data translation between Matlab and xilinx ISE simulator, i read solution given by u. I have written testbench for reading file (.txt) which contains matlab data and result of simulation i stored in again text file that i read in matlab for analysis of result . My problem is matlab works with floating point and ISE with fixed point . I want to read .wav file from matlab into ISE simulator. pl. tell me how to convert floating point(double)values of .wav file into fixed point(binary string) so as to store it in text file and again how to convert fixed point(binary string) into floating point(double)values for matlab analysis. I need solution very argently.

thank u. in advance.
anuja